Crystal CS4231A, Manual

Page: 19 / 76

higher frequencies, but any crystal with the
above specifications should suffice. The standard
crystals for audio are:
XTAL1: 24.576 MHz
Fundamental Mode
Parallel Resonant, C
L
= 20 pF
XTAL2: 16.9344 MHz
Fundamental Mode
Parallel Resonant, C
L
= 20 pF
These crystal frequencies support the standard
sample frequencies listed in Table 7.
External CMOS clocks may be connected the
crystal inputs (XTAL1I, XTAL2I) in lieu of the
crystals. When using external CMOS clocks, the
XTAL out pins should be left floating. Extreme
care should be used when laying out a board us-
ing external clocks since coupling between
clocks can degrade analog performance.
Power Down - PDWN
The PDWN signal places the CS4231A into
maximum power conservation mode. When
PDWN goes low, any reads of the codec’s paral-
lel interface return 80 hex, all analog outputs are
muted, and the voltage reference then slowly de-
cays to ground. When PDWN is brought high, a
full calibration cycle automatically occurs. While
the codec is initializing, any reads from the par-
allel interface will return 80 hex and writes will
be ignored. When initialization is completed, the
registers will contain their reset value as stated
in the register section of the data sheet. The
CS4231A contains an internal "Power On Reset"
signal that causes a proper initialization at power
up time. Therefore, if no power down mode is
needed, PDWN can be tied permanently to
VD3/4.
DBEN/DBDIR
If needed, the DBEN and DBDIR pins can con-
trol an external data buffer to the CS4231A. The
CS4231A contains 16 mA bus drivers so the ex-
ternal data buffer is only needed when driving a
full 24 mA bus. DBEN enables the external driv-
ers and DBDIR controls the direction of the data
flow. Both signals are normally high, where
DBDIR high points the transceiver towards the
codec and low points the transceiver towards the
data bus. See Figure 1 for a typical connection
diagram.
SOFTWARE DESCRIPTION
The CS4231A must be in Mode Change Enable
Mode (MCE=1) before any changes to the Inter-
face Configuration register (I9), the Sample
Frequency (lower four bits) in the Fs & Playback
Data Format register (I8), or the serial port bits
(SF1, SF0, SPE) in the Alternate Feature Enable
I register (I16) are allowed. The actual audio
data formats, which are the upper four bits of I8
for playback and I28 for capture, can be changed
by setting MCE (R0) or PMCE/CMCE (I16)
high. The exceptions are CEN and PEN which
can be changed "on-the-fly" via programmed I/O
writes to these bits. All outstanding DMA trans-
fers must be completed before new values of
CEN or PEN are recognized.
Power-Down and Initialization
To put the CS4231A into a power-down mode,
the PDWN pin is pulled low. In this state the
host interface reads 80h indicating that it is un-
able to respond and all analog circuits are turned
off.
To let the CS4231A go through its reset initiali-
zation the PDWN pin should be set high. This
CS4231A
DS139PP2 19