output clocks will stretch, but will not have any
glitches. This allows the serial port to operate
through a sample frequency change.
The first format - SPF0, shown in Figure 6, is
called 64-bit enhanced. This format has 64
SCLKs per frame with a one bit period wide
FSYNC that precedes the frame. The first 16 bits
FSYNC
SCLK
SDOUT
15 14 13
12
...
16 Bits
Left Data
0
15 14
...
0
16 Bits
Right Data
8 zeros
SDIN
15 14 13
12
...
16 Bits
Left Data
0
15 14
...
0
16 Bits
Right Data
INT = Interrupt Bit
CEN = Capture Enable
PEN = Playback Enable
OVR = Left Overrange or
Right Overrange
INT
7 zeros
CEN PEN OVR
13 zeros
32 Bits
...
Figure 6. 64-bit enhanced mode (SF1,0 = 00)
FSYNC
Left Data
SCLK
SDOUT/
15 14 13
0
...
15 14 13
0
...
15
Right Data
16 Clocks
16 Clocks
16 Clocks
16 Clocks
SDIN
Figure 7. 64-bit mode (SF1,0 = 01)
SCLK
FSYNC
Left Data
SDOUT/
15 14 13
0
...
16 Clocks
15 14 13
0
...
16 Clocks
15
Right Data
32 No-Clock bit periods
...
Left Data
14
...
...
SDIN
Figure 8. 32-bit mode (SF1,0 = 10)
CS4231A
DS139PP2
17
Summary of Contents for CS4231A
Page 63: ...Figure 1 CS4231 Aux1 In CDB4231 4248 DS111DB7 63 ...
Page 64: ...Figure 2 Microphone In Figure 3 Mono Speaker Out CDB4231 4248 64 DS111DB7 ...
Page 65: ...Figure 4 Line In CDROM In Aux2 CDB4231 4248 DS111DB7 65 ...
Page 66: ...Figure 5 Line Headphone Out CDB4231 4248 66 DS111DB7 ...
Page 67: ...Figure 6 Address Decode and Board ID CDB4231 4248 DS111DB7 67 ...
Page 68: ...Figure 7 Analog Power Buffer CDB4231 4248 68 DS111DB7 ...
Page 72: ...Figure 8 Silk Screen CDB4231 4248 72 DS111DB7 ...
Page 73: ...Figure 9 Component Side Top 1st Layer CDB4231 4248 DS111DB7 73 ...
Page 74: ...Figure 10 Solder Side Bottom 4th Layer CDB4231 4248 74 DS111DB7 ...
Page 75: ...Figure 11 Ground 2nd Layer Inverse CDB4231 4248 DS111DB7 75 ...
Page 76: ...Figure 12 Power 3rd Layer Inverse CDB4231 4248 76 DS111DB7 ...