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During initialization and power down, this regis-
ter can NOT be written and is always read
10000000 (80h)

PD7-PD0

Playback Data Port. This is the control
register where playback data is
written during programmed IO data
transfers.

Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read and the current sam-
ple is sent to the DACs via the FIFOs.

Indirect Mapped Registers

These registers are accessed by placing the ap-
propriate index in the Index Address register
(R0) and then accessing the Indexed Data regis-
ter (R1). All reserved bits should be written zero
and may be 0 or 1 when read. Indirect registers
16-31 are only available when the MODE2 bit in
MODE and ID register (I12) is set.

LAG3-LAG0

Left ADC Gain. The least significant
bit repr1.5 dB, with
0000 = 0 dB. See Table 4.

LMGE

Left Mic Gain Enable: This bit enables
the 20 dB gain stage of the left mic
input signal, LMIC.

LSS1-LSS0

Left ADC Input Source Select. These
bits select the input source for the
left ADC channel.

0 - Left Line: LLINE
1 - Left Auxiliary 1: LAUX1
2 - Left Microphone: LMIC
3 - Left Line Output Loopback

This register’s initial state after reset is: 000x0000

RAG3-RAG0

Right ADC Gain. The least significant
bit repr1.5 dB, with
0000 = 0 dB. See Table 4.

RMGE

Right Mic Gain Enable: This bit
enables the 20 dB gain stage of the
right mic input signal, RMIC.

RSS1-RSS0

Right ADC Input Select. These bits
select the input source for the right
ADC channel.

0 - Right Line: RLINE
1 - Right Auxiliary 1: RAUX1
2 - Right Microphone: RMIC
3 - Right Line Out Loopback

This register’s initial state after reset is: 000x0000

LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain.

The least significant bit represents
1.5 dB, with 01000 = 0 dB. See Ta-
ble 5.

LX1M

Left Auxiliary #1 Mute. When set to 1,
the left Auxiliary #1 input, LAUX1, to
the mixer, is muted.

This register’s initial state after reset is: 1xx01000.

Playback I/O Data Register (R3, Write Only)

D7

D6

D5

D4

D3

D2

D1

D0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Left ADC Input Control (I0)

D7

D6

D5

D4

D3

D2

D1

D0

LSS1 LSS0 LMGE

res LAG3 LAG2 LAG1 LAG0

Right ADC Input Control (I1)

D7

D6

D5

D4

D3

D2

D1

D0

RSS1 RSS0 RMGE

res RAG3 RAG2 RAG1RAG0

Left Auxiliary #1 Input Control (I2)

D7

D6 D5

D4

D3

D2

D1

D0

LX1M res res LX1G4 LX1G3 LX1G2 LX1G1 LX1G0

CS4231A

DS139PP2

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Summary of Contents for CS4231A

Page 1: ...in TQFP SEPT 94 DS139PP2 1 Crystal Semiconductor Corporation P O Box 17847 Austin TX 78760 512 445 7222 Fax 512 445 7581 Parallel Interface Multimedia Audio Codec Semiconductor Corporation CS4231A This document contains information for a new product Crystal Semiconductor reserves the right to modify this product without notice Preliminary Product Information Mute Gain Gain Mux LMIC RMIC LLINE RLIN...

Page 2: ...1A REGISTER MAPPING 28 Physical Mapping 28 Index Address Register R0 29 Index Data Register R1 29 Status Register R2 RO 29 Capture I O Data Register R3 RO 30 Playback I O Data Register R3 WO 31 Left ADC Input Control I0 31 Right ADC Input Control I1 31 Left Auxiliary 1 Input Control I2 31 Right Auxiliary 1 Input Control I3 32 Left Auxiliary 2 Input Control I4 32 Right Auxiliary 2 Input Control I5 ...

Page 3: ...puts Line to Mic Inputs Line to AUX1 Line to AUX2 80 80 90 90 dB dB dB dB Interchannel Gain Mismatch Line Inputs Mic Inputs 0 5 0 5 dB dB Programmable Input Gain Span Line Inputs 21 5 22 5 dB Gain Step Size 1 3 1 5 1 7 dB ADC Offset Error 0 dB gain 10 100 LSB Full Scale Input Voltage MGE 1 MIC Inputs MGE 0 MIC Inputs LINE AUX1 AUX2 MIN Inputs 0 266 2 66 2 66 0 29 2 9 2 9 0 31 3 1 3 1 Vpp Vpp Vpp G...

Page 4: ... OLB 0 Notes 3 5 OLB 1 OUT MOUT 1 8 2 6 2 0 2 8 2 25 3 2 Vpp Vpp Gain Drift 100 ppm C Deviation from Linear Phase Note 1 1 Degree External Load Impedance 10 kΩ Mute Attenuation 0 dB 80 dB Total Out of Band Energy 0 6xFs to 100 kHz Note 1 45 dB Audible Out of Band Energy 0 6xFs to 22 kHz Fs 8kHz 60 dB Power Supply Power Supply Current Digital Operating Analog Operating Total Digital Power Down Anal...

Page 5: ...device Normal operation is not guaranteed at these extremes RECOMMENDED OPERATING CONDITIONS AGND DGND 0V all voltages with repect to 0V Parameter Symbol Min Typ Max Units Power Supplies Digital Analog VD1 VD4 VA1 VA2 4 75 4 75 5 0 5 0 5 25 5 25 V V Operating Ambient Temperature TA 0 25 70 C AUXILIARY INPUT MIXERS TA 25 C VA1 VA2 VD1 VD4 5V Input Levels Logic 0 0V Logic 1 VD1 VD4 1 kHz Input Sine ...

Page 6: ... D 7 0 I0 16 0 mA All Others I0 4 0 mA VOL 0 4 0 4 V V Input Leakage Current Digital Inputs 10 10 µA Output Leakage Current High Z Digital Outputs 10 10 µA DIGITAL FILTER CHARACTERISTICS Parameter Symbol Min Typ Max Units Passband 0 0 40xFs Hz Frequency Response 0 5 0 2 dB Passband Ripple 0 0 4xFs 0 1 dB Transition Band 0 40xFs 0 60xFs Hz Stop Band 0 60xFs Hz Stop Band Rejection 74 dB Group Delay ...

Page 7: ...ded tDRHD 0 25 ns Time between rising edge of WR or RD to next falling edge of WR or RD tBWND 80 ns Data hold from RD rising edge tDHD1 0 20 ns DAK hold from WR rising edge DAK hold from RD rising edge tDKHDa tDKHDb 25 25 ns ns DBEN or DBDIR active from WR or RD falling edge tDBDL 40 ns PDWN pulse width low tPDWN 200 ns Crystals XTAL1I XTAL2I frequency Notes 1 7 8 25 6 MHz XTAL1I XTAL2I high time ...

Page 8: ...DDV t DKSUa t STW CDRQ CDAK DBEN D 7 0 RD DBDIR t DBDL 8 Bit Mono DMA Read Capture Cycle SDIN SDOUT t pd1 t s1 t h1 MSB Left SCLK t pd2 t pd2 FSYNC t sckw MSB Left t pd2 FSYNC SF1 0 01 10 SF1 0 00 Serial Port Timing CS4231A 8 DS139PP2 ...

Page 9: ...t Mono DMA Write Playback Cycle RIGHT HIGH BYTE LEFT LOW BYTE t BWDN D 7 0 RD WR CDRQ PDRQ CDAK PDAK 8 Bit Stereo or 16 Bit Mono DMA Cycle D 7 0 LOW BYTE t BWDN HIGH BYTE RD WR CDRQ PDRQ LEFT SAMPLE RIGHT SAMPLE HIGH BYTE LOW BYTE CDAK PDAK 16 Bit Stereo or ADPCM DMA Cycle CS4231A DS139PP2 9 ...

Page 10: ... 7 0 A 1 0 tCSSU tCSHD tDHD1 tRDDV tADSU tADHD tSUDK1 tSUDK2 tDBDL tDBDL I O Read Cycle CDRQ PDRQ CDAK PDAK CS DBEN DBDIR WR D 7 0 A 1 0 tCSSU tCSHD tDHD2 t SUDK2 tADSU tADHD t WDSU tSUDK1 tSTW high tDBDL I O Write Cycle CS4231A 10 DS139PP2 ...

Page 11: ... RAUX2 46 0 33 µF MIN XCTL0 XCTL1 56 58 SAI SAO IOWC IORC A1 A0 WR RD 60 61 9 10 CS 59 SA 19 2 AEN Address Decode 18 1 µF LOUT 40 47kΩ 1 µF ROUT 41 47kΩ 47 1 µF MOUT Board Analog Ground 26 31 RFILT LFILT 1000 pF NPO 1000 pF NPO VA1 VA2 15 7 1 35 1 µF 5V Supply Ferrite Bead 0 1 µF 0 1 µF 2 0Ω 19 0 1 µF 36 0 1 µF 5V Analog preferred If a separate 5V analog supply is available attach here and remove ...

Page 12: ...a zero to bit IA4 of the Index Address register R0 the CS4231A is backwards compatible with the CS4248 and the AD1848 Mixer Attenuation Control on Line Input The CS4231A adds mixer attenuation control for the LINE inputs which are then summed into the output mixer This fourth input to the mixer completes the recommended mixer configuration for MPC Level 2 compliance The LINE mix register provides ...

Page 13: ... jack as possible to minimize noise coupling Mono Input with Attenuation and Mute The mono input MIN is useful for mixing the output of the beeper timer chip provided in all PCs with the rest of the audio signals The attenuation control allows 16 levels in 3dB steps In addition a mute control is provided The attenuator is a single channel block with the resulting signal sent to the output mixer wh...

Page 14: ...REFI for similar reasons The VREF pin is typically 2 1 V and provides a common mode signal for single supply external circuits VREF only supports DC loads and should be buffered if AC loading is needed For typical use a 0 47 µF capacitor should be con nected to VREF The signal to noise ratio of the microphone inputs can be improved by increas ing the capacitance on VREF to 10 µF DIGITAL HARDWARE D...

Page 15: ...host to assert data on the DATA lines and strobe the WR sig nal The CS4231A will latch data into the PIO register on the rising edge of the WR strobe The CS4231A CS signal should remain active until after completion of the read or write cycle I O cycles are the only type of cycle which can ac cess the internal control and status registers When reading or writing audio data via PIO the Status regis...

Page 16: ...n However the capture audio channel is now diverted to the playback channel This means that the capture DMA request occurs on the PDRQ pin and the PDAK pin is used to acknow ledge the capture request In MODE 2 the capture data format is always set in register I28 Note simultaneous capture and playback cannot occur in SDC mode If both playback and cap ture are enabled the default will be playback I...

Page 17: ...s Right Data 8 zeros SDIN 15 14 13 12 16 Bits Left Data 0 15 14 0 16 Bits Right Data INT Interrupt Bit CEN Capture Enable PEN Playback Enable OVR Left Overrange or Right Overrange INT 7 zeros CEN PEN OVR 13 zeros 32 Bits Figure 6 64 bit enhanced mode SF1 0 00 FSYNC Left Data SCLK SDOUT 15 14 13 0 15 14 13 0 15 Right Data 16 Clocks 16 Clocks 16 Clocks 16 Clocks SDIN Figure 7 64 bit mode SF1 0 01 SC...

Page 18: ...ection and degrading analog performance The VD1 and VD2 pins are isolated from the rest of the digital power pins and provide digital power for the asynchronous parallel bus These two pins can be connected directly to the digital power supply VD3 and VD4 digital power supply pins provide power to the internal digital section of the codec and should be optimally quieter than VD1 and VD2 This can be...

Page 19: ...mode is needed PDWN can be tied permanently to VD3 4 DBEN DBDIR If needed the DBEN and DBDIR pins can con trol an external data buffer to the CS4231A The CS4231A contains 16 mA bus drivers so the ex ternal data buffer is only needed when driving a full 24 mA bus DBEN enables the external driv ers and DBDIR controls the direction of the data flow Both signals are normally high where DBDIR high poin...

Page 20: ...ull duplex and an ADC data format change is desired This is the only calibration mode that does not affect the DACs i e mute the DACs at some point Changing from any other calibration mode to No Calibration mode will take 40 sample periods to complete how ever subsequent MCE cycles will take 0 sample periods Converter Calibration CAL1 0 01 This calibration mode calibrates the ADCs and DACs but doe...

Page 21: ...LE bit I17 should be set When set both crystals are kept running thereby pro viding the fastest switching time 80h never appears between sample frequencies When XTALE is cleared the unused crystal is powered down to minimize noise coupling This causes 80h to appear after leaving an MCE cycle until the newly selected crystal is operational XTALE and the No Calibration mode I9 provide the fastest sw...

Page 22: ...complement is the standard method of repre senting 16 bit digital audio This format gives 96 dB theoretical dynamic range and is the standard for compact disk audio players This format uses the value 32768 8000h to repre sent maximum negative analog amplitude while 32767 7FFFh represents maximum positive analog amplitude 8 bit Unsigned The 8 bit unsigned format is commonly used in the personal com...

Page 23: ...me 0 7 8 15 16 23 24 31 RIGHT LEFT RIGHT LEFT Figure 13 8 bit Stereo Unsigned Audio Data sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 32 bit Word Time 0 15 16 31 24 23 8 7 MONO MONO Figure 14 16 bit Mono Signed Little Endian Audio Data sample 3 sample 3 sample 2 sample 2 sample 1 sample 1 32 bit Word Time 0 15 16 31 RIGHT LEFT 8 7 24 23 Figure 15 16 bit Stereo Signed Little Endian Audio D...

Page 24: ...ord Time sample 2 sample 2 sample 1 sample 1 sample 3 sample 3 RIGHT Figure 17 4 bit Stereo ADPCM Audio Data sample 2 sample 2 sample 1 sample 1 sample 3 sample 3 sample 4 sample 4 8 15 0 7 31 16 23 24 MONO LO MONO HI MONO LO MONO HI 32 bit Word Time Figure 18 16 bit Mono Signed Big Endian Audio Data sample 1 sample 1 sample 1 sample 1 sample 2 sample 2 sample 2 sample 2 8 15 0 7 31 16 23 24 RIGHT...

Page 25: ...t ACF I23 should be set When set the ADPCM algorithm will continue to oper ate until a complete word 4 bytes is written to the FIFO Then the ADPCM s block accumulator and step size will be frozen The user is required to read the FIFO until empty at which time the requests will stop When ACF is cleared the ADPCM adaptation will continue When PEN is 0 playback disabled the ADPCM block s accumulator ...

Page 26: ...ayback data to the DACs in MODE 2 In MODE 1 or when SDC 1 these registers I14 15 are used for both playback and capture When the playback Current Count register rolls under the Playback Interrupt bit PI I24 is set causing the INT bit R2 to be set The interrupt is cleared by a write of any value to the Status register R2 or writing a 0 to the Playback Interrupt bit PI I24 When SDC 1 PI re flects th...

Page 27: ...eature Status register I24 Since the timer will continue counting down while an interrupt is pending interrupts will be generated at fixed time intervals regardless of the time required to service the interrupt assuming the interrupt is serviced before the next timer interrupt is gener ated Interrupts The INT bit of the Status register R2 always reflects the status of the CS4231A internal inter ru...

Page 28: ...specifications The CS4231A powers up into the reset state which is defined as MODE 1 MODE 1 is backwards compatible with the CS4248 and only allows access to the first 16 indirect registers Setting the MODE2 bit in the MODE and ID register I12 enables MODE 2 which allows access to indirect regis ters 16 through 31 and enables all the features of the CS4231A Addr Register Name R0 0 Index Address re...

Page 29: ...er CANNOT be written and always reads 10000000 80h ID7 ID0 Indexed Data register These bits are the indirect register referenced by the Indexed Address register R0 During initialization and power down this regis ter can NOT be written and is always read 10000000 80h INT Interrupt Status This indicates the status of the internal interrupt logic of the CS4231A This bit is cleared by any write of any...

Page 30: ...te of the channel In ADPCM it indi cates along with CL R which one of four ADPCM bytes is waiting 0 Lower or 1 3 ADPCM byte waiting 1 Upper any 8 bit mode or 2 4 ADPCM byte waiting Note on PRDY CRDY These two bits are de signed to be read as one when action is required by the host For example when PRDY is set to one the device is ready for more data or when the CRDY is set to one data is available...

Page 31: ... Left ADC Input Source Select These bits select the input source for the left ADC channel 0 Left Line LLINE 1 Left Auxiliary 1 LAUX1 2 Left Microphone LMIC 3 Left Line Output Loopback This register s initial state after reset is 000x0000 RAG3 RAG0 Right ADC Gain The least significant bit represents 1 5 dB with 0000 0 dB See Table 4 RMGE Right Mic Gain Enable This bit enables the 20 dB gain stage o...

Page 32: ...et is 1xx01000 LDA5 LDA0 Left DAC Attenuator The least signifi cant bit represents 1 5 dB with 000000 0 dB See Table 6 LDM Left DAC Mute When set to 1 the left DAC output to the mixer will be muted This register s initial state after reset is 1x000000 RDA5 RDA0 Right DAC Attenuator The least signifi cant bit represents 1 5 dB with 000000 0 dB See Table 6 RDM Right DAC Mute When set to 1 the right ...

Page 33: ...nd capture In MODE 2 this bit is only used for playback and the capture format is independently selected via I28 MCE R0 or PMCE I16 must be set to modify S M See Changing Audio Data Formats section for more details 0 Mono 1 Stereo The C L FMT1 and FMT0 bits set the audio data format as shown below In MODE 1 FMT1 which is forced low FMT0 and C L are used for both play back and capture In MODE 2 the...

Page 34: ...ode only the playback will occur See the DMA section for further ex planation 0 Dual DMA channel mode 1 Single DMA channel mode CAL1 0 Calibration These bits determine which type of calibration the CS4231A performs whenever the Mode Change Enable MCE bit R0 changes from 1 to 0 The number of sample periods required for calibra tion is listed in parenthesis 0 No calibration 0 40 the first time 1 Con...

Page 35: ... indicates the current status of the PDRQ and CDRQ pins of the CS4231A 0 CDRQ AND PDRQ are presently inactive 1 CDRQ OR PDRQ are presently active ACI Auto calibrate In Progress This bit indicates the state of calibration The length of time high is dependent on the calibration mode selected 0 Calibration not in progress 1 Calibration is in progress PUR Playback underrun This bit is set when playbac...

Page 36: ...he 8 most significant bits of the 16 bit Playback Base register Reads from this register return the same value which was written The Current Count registers cannot be read When set for MODE 1 or SDC this register is used for both the Play back and Capture Base registers This register s initial state after reset is 0000000 PLB7 PLB0 Lower Base Bits This register is the lower byte which represents t...

Page 37: ...nalog out put level When clear analog line outputs are attenuated 3 dB 0 Full scale of 2 Vpp 3 dB 1 Full scale of 2 8 Vpp 0 dB This register s initial state after reset is 00000000 HPF High Pass Filter This bit enables a DC blocking high pass filter in the digital filter of the ADC This filter forces the ADC offset of 0 0 disabled 1 enabled XTALE Crystal Enable When set both crystals are always ac...

Page 38: ...B4 PUB3 PUB2 PUB1 PUB0 15 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0 16 OLB TE CMCE PMCE SF1 SF0 SPE DACZ 17 TEST TEST TEST TEST APAR XTALE HPF 18 LLM LLG4 LLG3 LLG2 LLG1 LLG0 19 RLM RLG4 RLG3 RLG2 RLG1 RLG0 20 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 21 TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0 22 23 ACF 24 TI CI PI CU CO PO PU 25 V2 V1 V0 CID2 CID1 CID0 26 MIM MOM MBY MIA3 MIA2 MIA1 MIA0 27 28 FMT1 FMT0 C L S M 29 30...

Page 39: ... 0 dB 1 0 0 0 1 3 0 dB 2 0 0 1 0 6 0 dB 3 0 0 1 1 9 0 dB 12 1 1 0 0 36 0 dB 13 1 1 0 1 39 0 dB 14 1 1 1 0 42 0 dB 15 1 1 1 1 45 0 dB Table 7 Mono Mixer Attenuation SS1 SS0 ADC Input Multiplexer 0 1 2 3 0 0 0 1 1 0 1 1 Line Auxiliary 1 Microphone Line Output Loopback Table 9 ADC Input Selector CFS2 CFS1 CFS0 XTAL1 24 576 MHz XTAL2 16 9344MHz 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0...

Page 40: ... 16 bit timer The time base is determined by the clock source selected from C2SL in I8 C2SL 0 divide XTAL1 by 245 24 576 MHz 9 969 µs C2SL 1 divide XTAL2 by 168 16 9344 MHz 9 92 µs This register s initial state after reset is 00000000 This register s initial state after reset is xxxxxxxx ACF ADPCM Capture Freeze When set the capture ADPCM accumulator and step size are frozen This bit must be clear...

Page 41: ...r by writing any value to the Status register R2 This register s initial state after reset is x0000000 V2 V0 Version number As enhancements are made to the CS4231A the version number is changed so software can distinguish between the different ver sions 100 All CS4231 revisions See Appendix A 101 CS4231A This Data Sheet CID2 CID0 Chip Identification Distinguishes between this chip and future chips...

Page 42: ...ster See Changing Audio Data Formats section for more details This register s initial state after reset is 0000xxxx This register s initial state after reset is xxxxxxxx CUB7 CUB0 Capture Upper Base This register is the upper byte which represents the 8 most significant bits of the 16 bit Capture Base register Reads from this this register returns the same value that was written This register s in...

Page 43: ...1 µF To achieve compatibility with the CS4231A 1 Correct spacing of pads will ensure that either 0 1 µF capacitors for the AD1848 rev K or 1000 pF NPO capacitors for the CS4231A may be installed 2 The CS4231A does not require the input anti aliasing filters included as an input R C for the AD1848 5 1kΩ and 560 pF The additional R C s can be used with the CS4231A if desired with no degrada tion in ...

Page 44: ...µ F VA BUS VD Figure 17 Recommended Decoupling Capacitor Positions Digital Ground Plane Codec digital signals Analog Ground Plane 1 8 PINS Codec analog signals Components CPU Digital Logic 5V Ferrite Bead Ground Connection CS4231A 65 8 Digital Pins Analog Pins Figure 16 Suggested Layout Guideline CS4231A 44 DS139PP2 ...

Page 45: ...ased on sample frequency selected all fre quency response plots x axis are shown from 0 to 1 where 1 is equivalent to Fs Therefore for any given sample frequency multiply the x axis values by the sample frequency selected to get the actual frequency 0 00 0 05 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 Input Frequency Fs 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 1 0 2 Magnitude dB Figure 19 ADC Passb...

Page 46: ...Input Frequency Fs 100 90 80 70 60 50 40 30 20 10 0 Magnitude dB Figure 23 DAC Transition Band 0 00 0 05 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 Input Frequency Fs 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 1 0 2 Magnitude dB Figure 22 DAC Passband Ripple 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 Input Frequency Fs 100 90 80 70 60 50 40 30 20 10 0 10 Magnitude dB Figure 21 DAC Filter Response CS...

Page 47: ...D1 VD1 D4 D5 D6 D7 DGND8 DBDIR DBEN WR CDRQ PDRQ VD3 DGND3 XTAL1I XTAL1O VD4 XTAL2I XTAL2O RFILT CDAK A0 PDAK PDWN DGND4 1 25 6 8 10 14 16 18 7 9 11 12 13 15 17 45 43 41 35 33 31 28 29 49 48 47 46 44 42 40 38 30 RD 75 74 72 70 56 73 69 71 57 76 100 77 79 85 87 89 91 93 99 98 92 90 88 86 84 78 59 60 61 62 SDIN FSYNC SCLK SDOUT CS4231A 100 pin TQFP Q Top View CS4231A DS139PP2 47 ...

Page 48: ... Q The assertion of this signal indicates that the codec is ready for more playback data The signal will remain asserted until the bytes needed for a playback sample have been transferred 11 13 15 17 19 21 23 25 1 3 5 7 9 67 65 63 61 35 33 31 29 27 37 39 41 43 45 47 49 51 53 55 57 59 VD1 DGND1 D4 D3 D5 D2 D6 D1 D7 D0 DGND8 VD2 DBEN DGND2 DBDIR A1 WR A0 RD CDAK CS CDRQ XCTL1 PDAK IRQ PDRQ XCTL0 VD3...

Page 49: ...and from the CS4231A DBEN Data Bus Enable Output Pin 63 L Pin 78 Q This pin indicates that the bus drivers attached to the CS4231A should be enabled This signal is active low DBDIR Data Bus Direction Output Pin 62 L Pin 77 Q This pin indicates the direction of the data bus transceiver High points to the CS4231A low points to the host bus This signal is normally high IRQ Host Interrupt Pin Output P...

Page 50: ... L Pin 28 Q Nominally 1 VRMS max analog input for the Right LINE channel centered around VREF The LINE inputs may be selected for A D conversion via the input multiplexer I1 A programmable gain block I19 also allows routing to the mixer LMIC Left Mic Input Pin 29 L Pin 30 Q Microphone input for the Left MIC channel centered around VREF This signal can be either 1 VRMS LMGE 0 or 0 1 VRMS LMGE 1 The...

Page 51: ...LB 0 the output is attenuated 3 dB and is a maximum of 0 707 VRMS ROUT Right Line Level Output Pin 41 L Pin 47 Q Analog output from the mixer for the right channel Nominally 1 VRMS max centered around VREF when OLB 1 I16 When OLB 0 the output is attenuated 3 dB and is a maximum of 0 707 VRMS MOUT Mono Output Pin 47 L Pin 57 Q When OLB 1 I16 MOUT is nominally 1 VRMS max analog output centered aroun...

Page 52: ...xternal circuitry although any AC loads should be buffered High internal gain microphone inputs S N ratio can be slightly improved by placing a 10µF capacitor on VREF VREFI Voltage Reference Internal Input Pin 33 L Pin 38 Q Voltage reference used internal to the CS4231A must have a 0 1 µF 10 µF capacitor with short fat traces to attach to this pin No other connections should be made to this pin LF...

Page 53: ...n of the codec except the parallel data bus These pins are connected to the substrate of the die as are the AGND pins Optimum layout is achieved by placing DGND3 4 7 8 on the analog ground plane with the AGND pins as shown in Figure 17 However other ground arrangements should yield adequate results NC VDD No Connect Pins 24 45 54 L These pins are no connects for the CS4231A When compatibility with...

Page 54: ... 60 dB added to compensate for the small input signal Use of a small input signal reduces the harmonic distortion components to insignificance when compared to the noise Units in dB Total Harmonic Distortion THD THD is the ratio of the test signal amplitude to the rms sum of all the in band harmonics of the test signal Interchannel Isolation The amount of 1 kHz signal present on the output of the ...

Page 55: ...lex and games software 2 Alternate Feature Enable I register I16 The PMCE and CMCE bits do not exist in the CS4231 These bits were added to enhance full duplex operation The serial audio data port and associated bits SF1 SF0 SPE do not exist on the CS4231 The serial audio data port was added to the CS4231A to allow DSP s and ASIC s to act as an audio coprocessor to the CS4231A 3 Alternate Feature ...

Page 56: ...ckage Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Angle MIN NOM MAX 0 077 100 0 00 0 14 15 70 15 70 0 40 0 30 0 0 12 0 0 20 0 127 16 00 14 0 16 00 14 0 0 50 0 50 1 66 0 26 0 177 16 30 16 30 0 60 0 70 A1 A c L1 T Notes 1 Dimensions in millimeters 2 Package body dimensions do not include mold protrusion which is 0 25 mm 3 Coplanarity is 0 004 in 4 Lead frame material is AL 42 or...

Page 57: ...e via the AUX2 inputs and support for the mono in and mono out capabilities of the CS4231 The CDB4231 also includes a serial port header to support the expanded features of the CS4231A Software that runs under Microsoft Windows 3 1 is also provided along with an extensive diagnostics pro gram ORDERING INFORMATION CDB4231 CDB4248 SEP 95 DS111DB7 57 Crystal Semiconductor Corporation P O Box 17847 Au...

Page 58: ...peration STEREO ANALOG INPUTS Three of the four external 1 8 stereo jacks are for analog inputs The stereo Mic I Microphone Input Figure 2 contains an op amp buffer with a gain of 18 dB providing a maximum full scale input to the evaluation board of 12 mV with the 20 dB boost inside the codec enabled For mi crophones that output signals larger than 12 mV the 20 dB gain block inside the codec can b...

Page 59: ...uality of the speaker used Much higher fidelity can be achieved by using a higher quality speaker Since the CS4248 does not have MIN and MOUT pins the CDB4248 board does not pro vide a cable and the SPEAKER IN and SPEAKER OUT headers are non functional SERIAL AUDIO DATA PORT The CS4231A contains a serial audio data port that can pass audio data from the ADCs and to the DACs across the serial port ...

Page 60: ...the DACK Header J20 labeled DMA PLAY Figure 7 is the primary DMA channel used for both playback and capture on the CS4248 or CS4231 in SDC mode as well as playback on the CS4231 in full duplex operation Half Duplex Single DMA Channel The default configuration for the CDB4231 is full duplex When the evaluation board is config ured for half duplex both jumpers on the DMA CAPTURE header J1 Figure 7 S...

Page 61: ... that check for a WSS board will read the board ID and assume that the auto se lect register needs to be loaded The auto select register only allows certain combinations which must be adhered to when using the evaluation board with this software Therefore to run 100 compatible Windows Sound System WSS software the IRQ and DMA selection must be made from the follow ing INT 7 default 10 11 Half Dupl...

Page 62: ...mper settings Since the board does not contain the extra hardware needed for software configuration of the IRQ and DMA channel the Auto Installation mode of the Microsoft WSS software is not supported The Microsoft WSS hardware and software driv ers do not use all the analog inputs The only hardware supported by the Microsoft WSS hard ware and software are a mono microphone input set jumper on J35...

Page 63: ...Figure 1 CS4231 Aux1 In CDB4231 4248 DS111DB7 63 ...

Page 64: ...Figure 2 Microphone In Figure 3 Mono Speaker Out CDB4231 4248 64 DS111DB7 ...

Page 65: ...Figure 4 Line In CDROM In Aux2 CDB4231 4248 DS111DB7 65 ...

Page 66: ...Figure 5 Line Headphone Out CDB4231 4248 66 DS111DB7 ...

Page 67: ...Figure 6 Address Decode and Board ID CDB4231 4248 DS111DB7 67 ...

Page 68: ...Figure 7 Analog Power Buffer CDB4231 4248 68 DS111DB7 ...

Page 69: ...0 PLD just used for buffer PIN 19 RDID O Read ID register enable PIN 20 RESDRV I Global Reset PIN 21 CCS O Chip Select for Codec PIN 22 CRES O Inverted RESDRV to codec PWDN pin PIN 23 DBEN I Data Bus Enable from codec Boolean Equation Segment EQUATIONS BA0 A0 RDID A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 AEN IOR X1 X0 530 533 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 AEN IOR X1 X0 604 607 A11 A10 A9 A8 A7 A6 A5 A4 A...

Page 70: ... 5 RDID I Read ID chip select from the AD31 PLD PIN 6 INT PIN 7 NC PIN 8 NC PIN 9 NC PIN 10 NC PIN 11 NC PIN 13 SBHE I PIN 14 D0 O Data Bus Enabled for RDID PIN 15 D1 O Places Read on the data bus PIN 16 D2 O PIN 17 D3 O PIN 18 D4 O PIN 19 D5 O PIN 20 D6 O PIN 21 D7 O PIN 22 ACCESS O True after first read of the codec PIN 23 RLYEN O Relay Enable Boolean Equation Segment EQUATIONS D0 GND D0 TRST RD...

Page 71: ...ACCESS ACCESS CRES CCS BIOR CRES RLYEN ACCESS MUTE Board ID PLD ID31 continued CDB4231 4248 DS111DB7 71 ...

Page 72: ...Figure 8 Silk Screen CDB4231 4248 72 DS111DB7 ...

Page 73: ...Figure 9 Component Side Top 1st Layer CDB4231 4248 DS111DB7 73 ...

Page 74: ...Figure 10 Solder Side Bottom 4th Layer CDB4231 4248 74 DS111DB7 ...

Page 75: ...Figure 11 Ground 2nd Layer Inverse CDB4231 4248 DS111DB7 75 ...

Page 76: ...Figure 12 Power 3rd Layer Inverse CDB4231 4248 76 DS111DB7 ...

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