Crystal CS4231A, Manual

Page: 43 / 76

GROUNDING AND LAYOUT
Fi g ur e 1 6 is a sugg ested l ayo ut for th e
CS4231A. Similar to other Crystal codecs, it is
recommended that the device be located on a
se pa ra t e a na l og gr ou n d pl a ne . Wi th th e
CS4231A’s parallel data interface, however, opti-
mum performance is achieved by extending the
digital ground plane across pins 65 through 68
and pins 1 through 8. Pins 2 and 8 are grounds
for the data bus and should be electrically con-
nected to the digital ground plane which will
minimize the effects of the bus interface due to
transient currents during bus switching. Figure
17 shows the recommended positioning of the
decoupling capacitors. The capacitors must be
on the same layer as, and close to, the CS4231A.
The vias shown go through to the ground plane
layer. Vias, power supply traces, and VREF
traces should be as large as possible to minimize
the impedance.
COMPATIBILITY WITH AD1848
The CS4231A is compatible with the AD1848
rev. J silicon, the CS4231, and the CS4248 in
terms of the applications circuit. The AD1848
rev K requires 0.1
µ
F capacitors (not 1000 pF)
on pins 26 and 31. The CS4231A requires
1000 pF NPO-type capacitors on filter pins 26
and 31 (not 0.1
µ
F). To achieve compatibility
with the CS4231A:
1. Correct spacing of pads will ensure that
either 0.1
µ
F capacitors (for the AD1848
rev K) or 1000 pF NPO capacitors (for
the CS4231A) may be installed.
2. The CS4231A does not require the input
anti-aliasing filters included as an input
R/C for the AD1848 (5.1k
Ω
and 560 pF).
The additional R/C’s can be used with
the CS4231A if desired, with no degrada-
tion in performance.
3. Although optimum performance is
achieved using the ground plane shown
in Figure 16, any ground plane scheme
that achieves acceptable performance
with the AD1848 should work with the
CS4231A.
4. The AD1848 needs extra power and
ground pins. The power pins (V
DD
) are
pins 24, 45, and 54. The ground pins
(GNDD) are pins 25 and 44. The
CS4231A PLCC package does not use
these pins and the appropriate
power/ground connections can be made.
5. The Mono In/Mono Out pins do not exist
on the AD1848.
6. The AD1848 does not contain 16 mA bus
drivers. Therefore, buffers must be used.
7. MODE 2 and all associated features do
not exist on the AD1848.
8. The AD1848 does not contain the select-
able dither (DEN, I10)
9. The AD1848 is not available in a 100-pin
TQFP package.
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
CS4231A
DS139PP2 43