Crystal CS4231A, Manual

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CS4231A REGISTER MAPPING
The two address pins of the CS4231A allow ac-
cess to four 8-bit registers. Two of these registers
provide indirect access to more CS4231A regis-
ters via an index register. The other two registers
provide status information and allow audio data
to be transferred to and from the CS4231A with-
out using DMA cycles or indexing.
Physical Mapping
The PIO registers are I/O mapped via four loca-
tions. Two address pins provide access to all of
the CS4231A’s registers. The four direct registers
are shown in Table 1. The first two direct regis-
ters are used to access 32 indirect registers
shown in Table 2. As indicated by the arrows,
the Index Address register (R0) points to the in-
direct register that is accessed through the
Indexed Data register (R1).
This section describes all the direct and indirect
registers. Table 3 details a summary of each bit
in each register with Tables 4 through 10 illus-
trating the majority of decoding needed when
programming the CS4231A and are included for
reference. Tables 4 through 8 indicate gain set-
tings at internal nodes. If OLB= 1 then the
output will reflect the gain setting. If OLB= 0,
the output will be attenuated by 3 dB as indi-
cated in the specifications. The CS4231A
powers up into the reset state which is defined as
MODE 1. MODE 1 is backwards compatible
with the CS4248 and only allows access to the
first 16 indirect registers. Setting the MODE2 bit
in the MODE and ID register (I12) enables
MODE 2 which allows access to indirect regis-
ters 16 through 31 and enables all the features of
the CS4231A.
Addr. Register Name
R0 0 Index Address register
R1 1 Indexed Data register
R2 2 Status register
R3 3 PIO Data register
Table 1. Direct Registers
Index Register Name
I0 Left ADC Input Control
I1 Right ADC Input Control
I2 Left Aux #1 Input Control
I3 Right Aux #1 Input Control
I4 Left Aux #2 Input Control
I5 Right Aux #2 Input Control
I6 Left DAC Output Control
I7 Right DAC Output Control
I8 Fs & Playback Data Format
I9 Interface Configuration
I10 Pin Control
I11 Error Status and Initialization
I12 MODE and ID (MODE2 bit)
I13 Loopback Control
I14 Playback Upper Base Count
I15 Playback Lower Base Count
I16 Alternate Feature Enable I
I17 Alternate Feature Enable II
I18 Left Line Input Control
I19 Right Line Input Control
I20 Timer Low Base
I21 Timer High Base
I22 RESERVED
I23 Alternate Feature Enable III
I24 Alternate Feature Status
I25 Version / Chip ID
I26 Mono Input & Output Control
I27 RESERVED
I28 Capture Data Format
I29 RESERVED
I30 Capture Upper Base Count
I31 Capture Lower Base Count
Table 2. Indirect Registers
CS4231A
28 DS139PP2