Crystal CS4231A, Manual

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is the left word and the second 16 bits is the
right word. The last 32 bits contains four status
bits and 28 zeros. This is the only mode that
contains status information.
The second serial format - SPF1, shown in Fig-
ure 7, is called 64-bit mode. This format also has
64 SCLKs per frame, but has FSYNC transition-
ing high at the start of the left data word and
transitioning low at the start of the right data
word. Both the left and the right data word are
followed by 16 zeros.
The third serial format - SPF2, shown in Fig-
ure 7, is called 32-bit mode. This format
contains 32 SCLKs per frame wherein FSYNC
is high for the left channel and low for the right
channel. The absolute time is similar to the other
two modes but SCLK is stopped after the right
channel is finished until the start of the next
frame (stopped for 32 bit period times). This
mode is useful for DSPs that do not want the
interrupt overhead of the 32 unused bit periods.
As an example, if a DSP serial word length is 16
bits, then four interrupts will occur in SPF0 and
SPF1; whereas in SPF2 the DSP will only get
two interrupts.
Miscellaneous Signals
The power supply providing analog power
should be as clean as possible to minimize noise
coupling into the analog section and degrading
analog performance. The VD1 and VD2 pins are
isolated from the rest of the digital power pins
and provide digital power for the asynchronous
parallel bus. These two pins can be connected
directly to the digital power supply. VD3 and
VD4 digital power supply pins provide power to
the internal digital section of the codec and
should be optimally quieter than VD1 and VD2.
This can be achieved by using a ferrite bead as
shown in the typical connection diagram in Fig-
ure 1. Grounding is covered in the Grounding
and Layout section.
An interrupt pin, IRQ, is provided to allow for
host notification by the CS4231A. Since the in-
terrupt is mainly a software function, it is
described in more detail under the software sec-
tion.
Crystals / Clocks
Four pins have been allocated to allow the inter-
facing of two crystal oscillators to the CS4231A:
XTAL1I, XTAL1O, XTAL2I, XTAL2O. The
crystals should be designed as fundamental
mode, parallel resonant, with a load capacitor of
between 10 and 20 pF. The capacitors shown in
Figure 1, connected to each of the crystal pins,
should be twice the load capacitance specified to
the crystal manufacturer. The XTAL1 oscillator
is designed with slightly more gain to handle
0
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSB
LSB MSB
LSB MSB
X: SDIN - Don’t care, SDOUT - 0
Audio Word
Bits
16
8
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X X X
Figure 9. Serial Audio Data Justification
CS4231A
18 DS139PP2