Crystal CS4231A, Manual

Page: 49 / 76

PDAK - Playback Data Acknowledge, Input, Pin 13 (L), Pin 8 (Q).
The assertion of this active low signal indicates that the WR cycle occurring is a DMA write to
the playback buffer.
A<1:0> - Address Bus, Input, Pin 9, 10 (L), Pin 100, 1 (Q).
These address pins are read by the codec interface logic during an I/O cycle access. The state of
these address lines determines which register (R0-R3) is accessed.
RD - Read Strobe, Input, Pin 60 (L), Pin 75 (Q).
This signal defines a read cycle to the codec. The cycle may be an I/O cycle read, or the cycle
could be a read from the codec’s DMA sample registers.
WR - Write Strobe, Input, Pin 61 (L), Pin 76 (Q).
This signal indicates a write cycle to the codec. The cycle may be an I/O cycle write, or the
cycle could be a write to the codec’s DMA sample registers.
CS - Chip Select, Input, Pin 59 (L), Pin 74 (Q).
The codec will not respond to any I/O cycle accesses until this signal goes low. This signal is
ignored during the DMA transfers.
D<7:0> - Data Bus, Input/Output, Pin 65-68, 3-6 (L), Pin 84-87, 90-93 (Q).
These signals are used to transfer data to and from the CS4231A.
DBEN - Data Bus Enable, Output, Pin 63 (L), Pin 78 (Q).
This pin indicates that the bus drivers attached to the CS4231A should be enabled. This signal
is active low.
DBDIR - Data Bus Direction, Output Pin 62, (L), Pin 77 (Q).
This pin indicates the direction of the data bus transceiver. High points to the CS4231A, low
points to the host bus. This signal is normally high.
IRQ - Host Interrupt Pin, Output, Pin 57 (L), Pin 72 (Q).
This active high signal is used to notify the host of events which need servicing.
Serial Audio Port Pins
SDOUT - Serial Data Output, Pin 52 (L), Pin 62 (Q).
Enabled via SPE in I16, the serial data out pin outputs audio data bits, on the rising edge of
SCLK, from the ADCs in the audio data format selected. The serial audio data is always 16 bits
wherein the MSB of the different audio formats (16, 8 , 4 bit) is aligned with zero padding after
the LSB. When SPE is zero (disabled), this pin is held low.
SCLK - Serial Clock, Output, Pin 51 (L), Pin 61 (Q).
Enabled via SPE in I16, the serial clock outputs audio data bits on the rising edge of SCLK and
receives audio data on the falling edge of SCLK. Two different formats are supported: 64
SCLKs per frame, and 32 SCLKs per frame. When SPE is zero (disabled), this pin is held low.
CS4231A
DS139PP2 49