4. Function
CNT24-4(PCI)H
43
Other Function
Compare Register
Compare the count value of a corresponding channel with the compare register value. If these two
values match, set status bit "EQ" to "0" (remains 0 as long as they are in agreement). This register can be
set to any value from 0h to FFFFFFh. It is possible either to cause an interrupt or to output a one-shot
pulse to an external device when the two values match.
Digital Filter
The digital filter allows the counter to operate normally even when noise enters into pulses input to the
counter and/or into A-, B-, and Z-phase signals. The sampling clock cycle of the digital filter is
determined by clock setting data for the digital filter.
When the input signal is sampled with this sampling clock and if HIGH (or LOW) is detected for
duration of four continuous clocks, the digital filter outputs HIGH (or LOW) and communicates it to the
counter circuit.
The cycle can be set in a range of 0.1
µ
sec through 1,056.1
µ
sec.
All externally input signals (except for general-purpose input signals) are fetched through the digital
filter into the internal counter. They are fetched after a delay of four set-sampling-cycle clocks.
When initialized, externally input signals are fetched after a delay of 0.4
µ
sec.
* The same applies also to the LOW level.
Externally
input signal
Externally
input signal
Digital filter
Four set-sampling-cycle clocks
Input to the PC
Not valid
Valid
Input to the PC
Figure 4.8. Digital filter
CAUTION
-
The initial state is set to 0.1
µ
sec. (When the cycle is not specified, the cycle also defaults to
0.1
µ
sec.)
-
A delay of more than four set-cycle clocks may occur depending on noise.
-
If a level changes at a frequency faster than the set-sampling-clock cycle, that level change is
invalidated and not correctly counted. Be sure to input signals which are less than the input
frequency.
