ATOMSW
Priority
Level
IBGi
IBGM
lBBi
IBBM
Relevant
BPGi
BPGi
BPGi
BPGi
BPs
BPGM
BPGM
BPGM
BPBI
BPBi
BPBM
ATOMSW
The
ATOMSW
an
ATM
output
buffer-type
cell
switch
has
eight
input
ports
and
eight
output
ports
The
buffer
performs
9-bit
81-bit
for
SSO
parallel
processing
by
using
bit
slice
division
and
processing
one
bit
with
one
ATOM
buffer
large
scale integration
LSI
The
ATOMSW
resides
on
subboard
on
the
motherboard
Each
output
port
is
equipped
with
128-cell
buffer
The
CPU
logically
divides
each
output
buffer
into
three
FIFO
cell
queues
The
first
FJFO
queue
is
48-cell
queue
for
an even-numbered
line
the
next
FIFO
queue
is
48-cell
queue
for
an odd-numbered
line
and
the
last
FIFO
queue
is
32-cell
queue
for both
lines Figure
B-3 shows
the
ATOMSW
block
diagram
ATOMSW
Cell
Switching
Function
For
point-to-point
connection
an output
port
is
selected
according
to
8-bit
routing
information
physical
address
PA2
in
the
switch-specific
overhead
SSO
The
four
lower
bits
of the
PA2
designate
16 lines
For
multicast
connection
the multicast
channel
identifier
in
the
SSO
is
referenced
to
acquire
the
bitmap
information
on
the output ports preset in the bitmap
table.This
information
is
used
to
select
output
ports
where
the
PA2
content
is
saved
ATOMSW
Congestion
Control
Back
pressure
guaranteed
BPGi
is
output
when
the
number
of
cells
stored
in output
line
FIFO
queue
exceeds
guaranteed
threshold
and back
pressure
best
effort
BPBi
is
output
when
best
effort
threshold
is
exceeded
Likewise
back
pressure guaranteed
multicast
BPGM
is
output
when
the
number
of
cells
stored
in multicast
FIFO
queue
exceeds
multicast
guaranteed
threshold
and
back
pressure
best
effort
multicast
BPBM
is
output
when
multicast
best
effort
threshold
is
exceeded
The
following
list
gives these
threshold
values
Guaranteed
threshold
32
allowable
range
0-48
Best
effort
threshold
24
allowable
range
0-48
Multicast
guaranteed
threshold
16
allowable
range
0-32
Multicast
best
effort
threshold
allowable
range
0-32
When
back
pressure
BP
signal
is
output up
to
two
cells
are input
to
each
port
and
cell
input
halts
at
every
port
When
BPi
is
received
from
output
line
cell
output
to
line
halts
B-4
Cisco HyperSwitch
A100
User
Guide