Chroma 66203, User Manual

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Appendix A Using Control Signal Input/Output Terminal
A-1
Appendix A Using Control Signal
Input/Output Terminal
The rear panel of the 66203/66204 Digital Power Meter has a 24-pin D-type terminal for
external trigger signal and external Pass/Fail display. The table below lists the pin
definition:
Limit_Trigger and Is_Trigger
The internal wiring diagram of Limit_Trigger and Is_Trigger is shown in Figure A-1. The
external TTL signals can be used to substitute the
TRIG/ENTER key on the front panel for
triggering. These two triggers are defined as falling edge trigger. Before Is Trigger is active,
it has to select the Is indicator first to enable the Is measurement mode. The Limit_Trigger
and Is_Trigger has about 100us to handle the noise false triggering. Be sure to take this
delay time into consideration for application.
FPGA
Reserve pin
nInrush_Trig
nLimit_Trig
66203/66204
GND
GND
1K Ω
1K Ω
GND
+5V
4.
7K
Ω
4.
7K
Ω
4.
7K
Ω
1K Ω
Figure A-1 Limit_Trigger & Is_Trigger Internal Wiring Diagram
Wiring for Pass + / Pass –
The internal wiring diagram of Pass + / Pass – is shown in Figure A-2. Pass + / Pass –
output is the two terminals of a one-gate Relay. When running GO/NG test, the Relay will
short-circuit if the test result is Pass. The Relay specification is 200VDC/0.5A Max.