Chroma 63600 Series, Operation & Programming Manual, Page: 232 / 258

Programmable DC Electronic Load 63600 Series Operation & Programming Manual
6-4
6.2.2 Channel Summary
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The Channel Summary registers summarize the channel status conditions up to 10
channels.
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When an enabled bit in the Channel Status Event register is set, it causes the
corresponding channel bit in the Channel Summary Event register to be set.
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Reading the Event register will reset it to zero.
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The Channel Summary Enable register can be programmed to specify the channel
summary event bit from the existing channels that is logically ORed to become Bit 2
(CSUM bit) in the Status Byte register.
6.2.3 Questionable Status
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The Questionable Status registers inform you one or more questionable status
conditions which indicate certain errors or faults have occurred to at least one channel.
Table 6-2 lists the questionable status conditions that are applied to the electronic load.
These conditions are same as the channel status conditions. Refer to Table 6-1 for a
complete description.
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When a corresponding bit of Questionable Status Condition register is set, it indicates
the condition is true.
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Program the PTR/NTR filter to select the way of condition transition in the Questionable
Status Condition register that will be set in the Event registers.
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Reading the Questionable Status Event register will reset it to zero.
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The Questionable status Enable register can be programmed to specify the
questionable status event bit that is logically ORed to become Bit 3 (QUES bit) in the
Status Byte register.
Table 6-2 Bit Description of Questionable Status
Mnemonic Bit Value Meaning
TE/OT 0 1 Temperature Error (Over temperature) .
OV 1 2 Over voltage .
CE/OC 2 4 Current Error (Over current) .
PE/OP 3 8 Power Error (Over power) .
RV 4 16 Reverse voltage on input .
SYNC 5 32 Synchronize timeout.
MAX LIM 6 64 Maximum sine wave current limit
FAN
7 128 FAN fail.
REMOTE
INHIBIT
8 256 Remote inhibit
6.2.4 Output Queue
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The Output Queue stores output messages until they are read from the electronic load.
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The Output Queue stores messages sequentially on a FIFO (First-In, First-Out) basis.
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It sets to 4 (MAV bit) in the Status Byte register when there are data in the queue.