CHEETAH Hardware User’s Manual
Imperx, Inc.
Rev. 1.6
6421 Congress Ave.
8/26/2016
Boca Raton, FL 33487
+1 (561) 989-0006
67 of 121
3.3.7 Programmable Frame Period Enable
This register enables the Fixed Frame Period
Address
:
0x0700
Data (0)
:
0 – disable
1 – enable
Data (31:1)
:
N/A
3.3.8 Output Pixel Clock Rate and Zero ROT
Pixel Clock Rate
This register sets the Pixel Clock Rate in MHz for the output
Address
:
0x0404
Data (8:0) :
<value> in MHz (32 to value in Pixel Clock Max register)
Data (31:9)
:
N/A
Zero Row Overhead Time (Zero-ROT)
This register controls Row Overhead Time. When disabled, one micro-second
is added to each line time. In CL two tap mode, Zero-ROT must be disabled.
Address
:
0x0708
Data (0)
:
0 – disable Zero-ROT
1 – enable
Data (31:1)
:
N/A
3.3.9 Fixed Frame Period
This register sets the frame period by adding V-Blanking Lines at the end of the
frame readout.
Address
:
0x0704
Data (15:0)
:
<value> frame period in lines (65,535 maximum)
Data (31:16)
:
N/A
