Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
Filename:
Number of pages:
Page:
00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
27
5.3.6. Delay
Lines
and Oscillators I/O
Delay Lines and Oscillators signals are as follows (see also § 5.5.5 and § 5.5.6):
Table 5.4: Delay Lines and Oscillators signals
PDL0_OUT
IN
1
Signal from PDL0 Output
PDL1_OUT
IN
1
Signal from PDL1 Output
DLO0_OUT
IN
1
Signal from DLO0 Output
DLO1_OUT
IN
1
Signal from DLO1 Output
PDL0_IN
OUT
1
Signal to PDL0
PDL1_IN
OUT
1
Signal to PDL1 Input
DLO0_GATE
OUT
1
Signal to DLO0 Input
DLO1_GATE
OUT
1
Signal to DLO1 Input
5.3.7. SPARE
Interface
These signals allow to set and read the status of SPARE pin present on the board.
Table 5.5: SPARE Interface signals
SPARE_OUT
OUT
12
SPARE Data Out
SPARE_IN
IN
12
SPARE Data In
SPARE_DIR OUT
1
SPARE
Direction
5.3.8. LED
Interface
These signals, when active for one clock cycle, allow to generate a blink of the relevant
Led.
Table 5.6: LED Interface signals
RED_PULSE
OUT
1
RED Led Pulse (active high)
GREEN_PULSE OUT
1
GREEN Led Pulse (active high)
5.4. Reference design description
The reference design preloaded into the USER FPGA is given as a design guide. It is a
full functional application of the usage of the board as a concidence and/or I/O register
unit. This reference design give access to A,B,C,G ports. So no mezzanine expansion
cards are needed in order to use this design.
The MODE register can be used to set the preferred operating mode. When the board is
switched on, the default operating mode is I/O Register mode.