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User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
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00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
34
D) updating of PDL1 delay via VMEbus:
Step 1: write 0x7 in the PDL_CONTROL register
Step2: write the delay value in the PDL_DATA register
GATE WIDTH (USING Delay Line Oscillators)
The GATEWIDTH register can be used to set the gate signal width on the G port (see
Delay Unit using DLOs, see § 5.5.6).
5.5.5.
Delay Unit using PDLs
The following diagram shows the implementation of the DELAY_UNIT using the one of
the two programmable delay lines (PDL) available on the boards.
'1'
COINC
STARTDELAY
PDLx_OUT
PDLx_IN
PDLx
PDL_PULSEOUT
STOPDELAY
CLR
CLK
D
Q
PULSE
GEN.
'1'
STOPDELAY
CLR
CLK
D
Q
MONOSTABLE
(360 ns
pulse)
Fig. 5.4: Delay Unit with PDLs
COINC
PDLx_OUT
STARTDELAY
PDL_PULSEOUT
STOPDELAY
PDLx_IN
Tp
Tmon
.
Fig. 5.5: PDLs Delay line timing
The pulse width generated using PDLs (Tp) can be adjusted setting the PDL delay using
either on-board dip switches or through register.
