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User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
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00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
14
Fig. 3.1: Timers diagram
The use of STARTx signals with timing shorter than those recommended is possible,
although the linearity on the set delay scale is no longer guaranteed.
3.1.2. Timer2,
Timer3
Each timer is made up of one digital circuit which produces a typical fixed time base with
10ns period and 50% duty cycle. These timers are proposed for generating any Gate
pulse > 10ns with a 10ns step. The following figure shows an example of a Gate
generation made with Timer2 and n.3 PULSE width.
Fig. 3.2: Gate pulse example
FPGA USER drives a /STARTx pulse and after T
EN
time FPGA USER will receive a
PULSEx clock signal. A counter with clock = PULSEx implemented in the FPGA USER,
allows to generate a pulse with programmable duration. It is possible to reduce to one
half (5ns) the counter step by advancing the counter on both sides of PULSEx. Since the
circuit is completely digital, no recovery time is necessary between one stop and the
following start: it is thus possible to generate multiple gate pulses with very high rate.
Timer2 and Timer3 can be used together for handling one single Gate pulse from
multiple overlapped triggers.
en
T
PULSE 2
/START 2
GATE
T
pd
COUNT 2
COUNT 0
COUNT 1
COUNT 2
T
T
period
width
offset
T
T
set
PULSE 0
START 0
GATE
Tdly= T Tset
Toffset = 30 ± 2ns
Tset = SETBINARY * 1ns
STARTx-WIDTHMIN = 320ns recommended
(22ns absolute min.)
STARTx-PERIODMIN = 640ns recommended
(46ns absolute min.)
