Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
Filename:
Number of pages:
Page:
00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
17
4. VME Interface
4.1. Register
address
map
The Address map for the Model V1495 is listed in Table 4.1. All register addresses are
referred to the Base Address of the board, i.e. the addresses reported in the Tables are
the offsets to be added to the board Base Address.
Table 4.1: Address Map for the Model V1495
ADDRESS REGISTER/CONTENT
ADDR
DATA
Read/Write
Base + 0x0000
÷
0x7FFC
USER FPGA Access
A24/A32
D16
R/W (*)
Base + 0x8000
Base + 0x8002
Base + 0x8004
Base + 0x8006
Base + 0x8008
Base + 0x800A
Base + 0x800C
Base + 0x800E
Base + 0x8010
Base + 0x8012
Base + 0x8014
Base + 0x8016
Base + 0x8018
Base + 0x8020
Base + 0x8100
÷
0x801FE
Control Register
Status Register
Interrupt Level
Interrupt Status-ID
Geo Address_Register
Module Reset
Firmware revision
Select VME FPGA Flash
(**)
VME FPGA Flash memory
(**)
Select USER FPGA Flash
(**)
USER FPGA Flash memory
(**)
USER FPGA Configuration
(**)
Scratch16
Scratch32
Configuration ROM
(**)
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D32
D16
R/W
R
R/W
R/W
R
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
(*)
Read/Write capability depends on USER FPGA implementation
.
(**) See § 5.7
4.1.1. Configuration
ROM
The following registers contain some module’s information according to the Table 3.2,
they are D16 accessible (read only):
•
OUI
:
manufacturer identifier (IEEE OUI)
•
Version
:
purchased
version
•
Board ID
:
Board identifier
•
Revision
:
hardware revision identifier
•
Serial MSB
:
serial number (MSB)
•
Serial LSB
:
serial number (LSB)
Table 4.2: ROM Address Map for the Model V1495
Description
Address
Content
checksum
0x8100
checksum_length2 0x8104
checksum_length1 0x8108
checksum_length0 0x810C
constant2 0x8110
