Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
Filename:
Number of pages:
Page:
00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
23
5.2.2. COIN_REFERENCE
Design
The COIN_REFERENCE design VHDL entity is the interface to the V1495HAL. If the
User wishes to use V1495HAL to develop his own application on the V1495 platform, the
VHDL entity must not be modified: this means that signals names and function of the
COIN_REFERENCE entity must be used, as shown in the following table:
Table 5.1: COIN_REFERENCE signals
PORT NAME
DIRECTION
WIDTH
DESCRIPTION
GLOBAL SIGNALS
NLBRES
IN
1
Async Reset (active low)
LCLK
IN
1
Local Bus Clock (40 MHz)
REGISTER INTERFACE
REG_WREN
IN
1
Write pulse (active high)
REG_RDEN
IN
1
Read pulse (active high)
REG_ADDR IN
16
Register
address
REG_DIN
IN
16
Data from CAEN Local Bus
REG_DOUT
OUT
16
Data to CAEN Local Bus
USR_ACCESS
IN
1
Current register access is
at user address space(Active high)
V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE
A_DIN
IN
32
In A (32 x LVDS/ECL)
B_DIN
IN
32
In B (32 x LVDS/ECL)
C_DOUT
OUT
32
Out C (32 x LVDS)
G_LEV
OUT
1
Output Level Select (0=>TTL; 1=>
NIM)
G_DIR
OUT
1
Output Enable (0=>Output, 1=>Input)
G_DOUT
OUT
2
Out G - LEMO (2 x NIM/TTL)
G_DIN
IN
2
In G – LEMO (2 x NIM/TTL)
V1495 Mezzanine Expansion Ports (PORT D,E,F) INTERFACE
D_IDCODE
IN
3
D slot mezzanine Identifier
D_LEV
OUT
1
D slot Port Signal Level Select
(the level selection depends on the
mezzanine expansion board mounted
onto this port)
