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User's Manual (MUT)

Mod. V1495 General Purpose VME Board

12/02/2010

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00117/04:V1495.MUTx/08 V1495_REV8.DOC

NAME

ADDRESS

DATA SIZING

ACCESS

NOTES

DEFAULT

selected delay line period (see

detailed description)

C_CONTROL_L 0x001A

D16

Port C control. When the port C is

configured to be an output under

controlled by this register.

X"0000"

C_CONTROL_H 0x001C

D16

Port C control. When the port C is

configured to be an output under

controlled by this register.

X"0000"

MODE

0x001E

D16

It configures the behaviour of the

system:

MODE[1:0]: DELAY SEL

MODE[3]: UNIT_MODE

‘0’: Coincidcence Unit

‘1’: I/O Register

MODE[4]:OPERATOR

‘0’: C= A AND B;

‘1’: C = A OR B;

MODE[5]:PULSE_MODE

See Description

X"0008"; --

Default : I/O

Mode.

SCRATCH

0x0020

D16

This register is available to test

read and write to a register.

X"5A5A"

G CONTROL

0x0022

D16

Only Bit 0 (G_CONTROL(0)) is

used in this reference design. It can

be used to select G output level:

‘0’: TTL

‘1’: NIM

X"0000"

D_CONTROL_L 0x0024

D16

X"0000"

D_CONTROL_H 0x0026

D16

X"0000"

D_DATA_L 0x0028 D16

X"0000"

D_DATA_H 0x002A D16

X"0000"

Summary of Contents for V1495

Page 1: ...Technical Information Manual MOD V1495 12 February 2010 Revision n 8 GENERAL PURPOSE VME BOARD NPO 00117 04 V1495 MUTx 08...

Page 2: ...responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any...

Page 3: ...ZZANINE BOARDS INSTALLATION 11 2 8 FRONT PANEL CONNECTOR CABLING 11 3 OPERATING MODES 13 3 1 TIMERS 13 3 1 1 Timer0 Timer1 13 3 1 2 Timer2 Timer3 14 3 2 FPGA PROGRAMMING 15 3 2 1 FPGA VME 15 3 2 2 FPG...

Page 4: ...4 REFERENCE DESIGN DESCRIPTION 27 5 5 REGISTER DETAILED DESCRIPTION 31 5 5 1 V1495 Front Panel Ports Registers PORT A B C G 31 5 5 2 V1495 Mezzanine Expansion Ports Registers PORT D E F 32 5 5 3 Dela...

Page 5: ...ROJECT BROWSER 39 FIG 5 12 QUARTUS II NETLIST 40 FIG 5 13 QUARTUS II HIERARCHICAL STRUCTURE 40 FIG 5 14 QUARTUS II COMPILER LAUNCHING 41 FIG 5 15 QUARTUS II COMPILING SUMMARY 41 LIST OF TABLES TABLE 1...

Page 6: ...herboard see 1 2 The channel interface can be expanded in the D E F sections by using up to 3 mezzanine boards see 2 6 and 2 7 which can be added choosing between the five types developed in order to...

Page 7: ...Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 7 1 2 Block Diagram Fig 1 1 Mod V1495 Block Diagram A B C 32 32 32 32 32 32 USER PROGRAMMABLE FPGA 4 4 BRIDGE FPGA VME interface...

Page 8: ...nnectors and fits into both VME standard and V430 backplanes 2 2 Power requirements The power requirements of the modules are as follows Table 2 1 Model V1495 and mezzanine boards power requirements P...

Page 9: ...Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 9 2 4 Front Panel SCALE R 16 CH Mod V560E Mod V1495 DTACK A D B A GENERAL PURPOSE VME BOARD 0 O U T 0 31 31 C F USER B E L V D S...

Page 10: ...ctable TTL IN Direct TTL OUT Direct NIM IN Invert NIM OUT Direct NIM TTL selectable Open 50ohm Rt selectable 250MHz LEMO 00 2 6 Mezzanine Specifications The five I O Mezzanine boards developed so far...

Page 11: ...Plug the mezzanine board into the 100 pin connector on the motherboard Fix the mezzanine board with the screws WARNING A Mounting Option is necessary in order to install three A395C mezzanine boards o...

Page 12: ...mber of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 12 The CAEN Mod A967 Cable Adapter allows to adapt each Robinson Nugent Multipin Connector into two 1 17 17 pin Header type male connectors...

Page 13: ...nput signals are not referred to a system clock As a consequence the gate signal will be generated without any time reference It is possible to use the implementation described above with the freedom...

Page 14: ...pulse example FPGA USER drives a STARTx pulse and after TEN time FPGA USER will receive a PULSEx clock signal A counter with clock PULSEx implemented in the FPGA USER allows to generate a pulse with p...

Page 15: ...cuted via VME The flash related to FPGA VME contains the firmware dedicated to the interface of the board with the FPGA USER and the VME bus such firmware is developed by CAEN The flash related to the...

Page 16: ...power on The flash memory contains one firmware image only Standard Fig 3 5 FPGA USER diagram FPGA VME aim is to handle the operation of FPGA USER which can be programmed on the fly i e without turnin...

Page 17: ...Interrupt Status ID Geo Address_Register Module Reset Firmware revision Select VME FPGA Flash VME FPGA Flash memory Select USER FPGA Flash USER FPGA Flash memory USER FPGA Configuration Scratch16 Scr...

Page 18: ...loaded into the Configuration ROM 4 2 Control Register Base Address 0x8000 read write D16 This register allows performing some general settings of the module Not used for VME FPGA Rev 0 0 Foreseen for...

Page 19: ...ing Fig 4 3 Geographical address register This register allows readback of the level of GEO pins for the selected board The register content is valid only for the VME64X board version The register con...

Page 20: ...oped and distributed by CAEN see 5 7 4 12 Select USER FPGA Flash Register Base Address 0x8012 read write D16 This register allows USER FPGA configuration update stored into on board flash memory via V...

Page 21: ...tion Register Base Address 0x8016 read write D16 This register allows the update of the USER FPGA configuration A write access to this register generates a configuration reload The configuration image...

Page 22: ...R FPGA to implement a Coincidence Unit I O Register Unit This design can be customised by the user in order to adapt its functionality to his own needs USER DEFINED LOGIC HARDWARE ABSTRACTION LAYER CA...

Page 23: ...tive low LCLK IN 1 Local Bus Clock 40 MHz REGISTER INTERFACE REG_WREN IN 1 Write pulse active high REG_RDEN IN 1 Read pulse active high REG_ADDR IN 16 Register address REG_DIN IN 16 Data from CAEN Loc...

Page 24: ...slot Data Out Bus F_IDCODE IN 3 F slot mezzanine Identifier F_LEV OUT 1 F slot Port Signal Level Select the level selection depends on the mezzanine expansion board mounted onto this port F_DIR OUT 1...

Page 25: ...e USER FPGA registers which can be accessed via VMEbus The COIN_REFERENCE module shows how to implement a set of registers The following table shows the registers map as it is provided Each register a...

Page 26: ...the piggy back board ports D E F The following table explains the available signals Table 5 2 V1495 Mezzanine Expansion Ports signals Port Signal Function Applies to D_DIR Selects direction Bidirectio...

Page 27: ...d read the status of SPARE pin present on the board Table 5 5 SPARE Interface signals SPARE_OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In SPARE_DIR OUT 1 SPARE Direction 5 3 8 LED Interface T...

Page 28: ...et to 0 an AND logic operation is applied to corresponding bits in Port A and B i e A 0 AND B 0 A 1 AND B 1 etc In this case a trigger is generated if corresponding A and B port bits are 1 at the same...

Page 29: ...us This register reflects B 31 16 bit status C_STATUS_L 0x0008 D16 RO Port C status This register reflects C 15 0 bit status C_STATUS_H 0x000A D16 RO Port C status This register reflects C 31 16 bit s...

Page 30: ...C is configured to be an output under register control see MODE register the status of C 31 16 is controlled by this register X 0000 MODE 0x001E D16 WO It configures the behaviour of the system MODE 1...

Page 31: ...delay though either on board switches or via VMEbus X 0001 Default PDL delay is set by on board dip switches PDL_DATA 0x0040 D16 RW X 0000 D_IDCODE 0x0042 D16 RO Read Slot D mezzazine ID Code ID Code...

Page 32: ...the status of the unmasked input and output ports A control register C_CONTROL is available to set the C port when the board is configured in I O register mode 5 5 2 V1495 Mezzanine Expansion Ports R...

Page 33: ...matically loaded By setting this bit to 0 the delay value cannot be changed PDL_DIR allows to select the source of data for PDL programming 0 the selected PDL has as delay value on its parallel progra...

Page 34: ...width on the G port see Delay Unit using DLOs see 5 5 6 5 5 5 Delay Unit using PDLs The following diagram shows the implementation of the DELAY_UNIT using the one of the two programmable delay lines...

Page 35: ...ernal signal is generated as the logic OR of PDL_IN and PDL_OUT so generating a pulse whose width is proportional to the PDL actual delay The PDL_PULSEOUT signal falling edge is used to reset the flip...

Page 36: ...5 6 Quartus II Web Edition Project The freely available Altera Quartus II it can be downloaded from the Altera Web site software must be used in order to generate a user firmware for the USER FPGA It...

Page 37: ...o verify the functionality of the project The reference design includes a minimum set of contraints in order to allow the design to perform the foreseen function The last important step is the generat...

Page 38: ...sion User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 38 Fig 5 9 Quartus II main menu Now select File Open...

Page 39: ...f Fig 5 11 Quartus II project browser Once the project is open the Project Navigator shows the following information There are 5 VHDL files filename vhd and a Verilog netlist listname vqm The referenc...

Page 40: ...pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 40 Fig 5 12 Quartus II netlist The first time the project is launched the hierarchy includes only the name of the head of the project v1495usr_demo...

Page 41: ...to launch the compiler by clicking on the red play button on the tool bar Fig 5 14 Quartus II compiler launching Quartus at this point launches in sequence the steps of the flow chart synthesis fittin...

Page 42: ...V1495 MUTx 08 V1495_REV8 DOC 42 42 5 7 Firmware upgrade It is possible to upgrade the board firmware via VME by writing the Flash for this purpose download the software package and the CVUpgrade tool...

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