Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. N957 8k Multi-Channel Analyzer
28/05/2012
6
NPO:
Filename:
Number of pages:
Page:
00105/04:N957x.MUTx/06 N957_REV6
35
20
3. Software interface
The module can be operated via a set of software accessible registers, whose
description is reported in the subsequent sections.
3.1 Register
map
REGISTER NAME
ADDRESS
MODE FUNCTION
STATUS 0x00
R
Status
register
CONTROL 0x01
R/W
Control
register
FWREV
0x02
R
FPGA firmware revision
FWDWLND
0x03
R/W
R/W configuration rom data
FLENA 0x04
R/W
Flash
enable
PULSER
0x05
R/W
SW pulse duration
DAC
0x06
R/W
DAC value setting
BLDIM
0x07
R/W
Data transfer block size
POTCTRL
0x08
R/W
Digital pot control register
CAL_SET
0x09
W
Digital pot bit set register
CAL_CLEAR
0x0A
W
Digital pot bit clear register
SCRATCH 0x0B
R/W
Scratch
BUFFER OCCUPANCY
0x0C
R
Buffer occupancy
SCALER_L
0x0D
R
Scaler (16 LSB)
SCALER_H
0x0E
R
Scaler (16 MSB)
TIMER_L
0x0F
R/W
Timer (16 LSB)
TIMER_H
0x10
R
Timer (16 MSB)
LIVETIME_L
0x11
R
Live Timer (16 LSB)
LIVETIME_H
0x12
R
Live Timer (16 MSB)
SW CLEAR
0x13
W
Software Clear
SW RESET
0x134
W
Software Reset
