Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. N957 8k Multi-Channel Analyzer
28/05/2012
6
NPO:
Filename:
Number of pages:
Page:
00105/04:N957x.MUTx/06 N957_REV6
35
14
GATE
PEAK section
Output
INPUT
BUSY
Output
Conversion
Logic
State
idle
settling
digitisa
tion
clear
idle
track
2
s
0.8
s
2
s
Peak detection
(absolute peak over threshold)
Fig. 2.5: Signal conversion timing External Gate mode
2.8.2 Pile Up Rejection
The PUR input signal prevents the ADC to store piled up events. It accepts NIM/TTL
(switch selected, see § 2.6.1) signal. To reject an event, the PUR signal must occur
before the conversion logic state Digitisation (before start of BUSY pulse) and must
overlap the BUSY output signal (see Fig. 2.6).
Auto-Gate
(Internal)
PEAK
section
Output
Input
Busy
Output
Conversion
Logic
State
Threshold
idle
settling
digitisa
tion
clear
idle
track
Peak detection
(first peak over threshold)
PUR
event
Rejected
Fig. 2.6: PUR timing for event rejection (Auto Gate mode)
