Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. N957 8k Multi-Channel Analyzer
28/05/2012
6
NPO:
Filename:
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Page:
00105/04:N957x.MUTx/06 N957_REV6
35
12
2.8.1 Analog to digital conversion timing
The signal conversion timing is shown in the following figures (Fig. 2.3, Fig. 2.4, Fig. 2.5
); the diagram includes five different logic states:
Idle
Track
(acquiring data phase)
Settling
(Settling time before ADC conversion)
Digitisation
(ADC Conversion)
Clear
(fast capacitor discharge in the peak section)
Idle state:
Auto Gate mode: the input signal after threshold starts the Track (acquiring data)
phase
External Gate mode: the occurrence of a GATE pulse starts the Track (acquiring
data) phase
Track
(acquiring data )
state
Auto Gate mode: in the Track state the PEAK output increases according to the
input signal. When the first peak is detected starts the Settling phase (where the
peak value is held by means of a capacitor)
External Gate mode: in the Track state the PEAK output increases according to
the input signal until the highest peak within the GATE ON is reached. When the
GATE signal become inactive starts the Settling phase (where the peak value is
held by means of a capacitor)
Settling
(Settling time before ADC conversion)
The peak value is held by means of a capacitor until the end of the digital conversion
(digitisation) The Settling state takes about 2 µs (settling time)
Digitisation state
During this phase the output of the PEAK section is converted by a 13 bit Fast ADC (the
phase takes 0.8
sec )
Clear
state
After the digital conversion, the clear phase takes place by a fast capacitor discharge
(about 2 µs) which makes the conversion logic idle again.
