Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. N957 8k Multi-Channel Analyzer
28/05/2012
6
NPO:
Filename:
Number of pages:
Page:
00105/04:N957x.MUTx/06 N957_REV6
35
24
3.17 Timer Low register (0x0F, r/w)
Bit
Name
Function
15..0 TIMER_L
Acquisition Real Time(bits 15..0); LSB=1ms. Enabled via Timers/scaler
enable FLAG (see § 3.3). A write access to this register allows to freeze the
values of Scaler L/H, Timer and Livetime L/H registers.
3.18 Timer High register (0x10, r)
Bit
Name
Function
15..0 TIMER _H
Acquisition Real Time (bits 31..16); LSB=1ms; enabled via Timers/scaler
enable FLAG (see § 3.3).
3.19 Livetime Low register (0x11, r)
Bit
Name
Function
15..0 LIVETIME _L
Acquisition Live Time (bits 15..0) ; LSB=1ms; enabled via Timers/scaler
enable FLAG (see § 3.3).
Auto Gate mode: counts only if board is not full and Conversion logic state
is Idle or Track.
External Gate mode: counts only if board is not full and Conversion logic
state is Track or Settling.
3.20 Livetime High register (0x12, r)
Bit
Name
Function
15..0 LIVETIME _H
Acquisition Live Time (bits 31..16) ; LSB=1ms; enabled via Timers/scaler
enable FLAG (see § 3.3).
Auto Gate mode: counts only if board is not full and Conversion logic state
is Idle or Track.
External Gate mode: counts only if board is not full and Conversion logic
state is Track or Settling.
3.21 Software Clear register (0x13, w)
Bit
Name
Function
15..0 SW CLEAR
Any value written to this register generates a software clear which erases
the buffer, timers and scalers
3.22 Software Reset register (0x14, w)
Bit
Name
Function
15..0 SW RESET
Any value written to this register generates a software reset which erases
the buffer, timers and scalers; moreover it resets the FLAG CLEAR and
reset Control FPGA state, see § 3.3
