Bull NovaScale 5 5 Series, User Manual, Page: 336 / 384

C-22
User’s Guide
IA–32
POST Codes
Meaning
0x009A Set the RS–232 base address.
Next, checkpoint 9Bh.
0x009B Perform any chipset or OEM initialization.
If needed check Coprocessor at checkpoint 0x009C else next, checkpoint
A2h.
0x009C Coprocessor test done. Next, checkpoint 9Dh.
0x009D Initialization after the Coprocessor test is complete.
Update equipment byte in CMOS and CMOS checksum.
Next, checkpoint A2h.
0x00A2 Display any SMART error messages.
Test for floppy drive.
Initialize POST error information for event logging.
Display any soft error messages. If errors occurred, then “Run Setup” dis-
played if hard disk error, CMOS time error, or cache error. Else display
“Press F1 to resume” and wait for F1 key to be pressed.
If CMOS bad or memory error occurred then
HALT! If POST diagnostic
switch enabled, then reboot.
Next, checkpoint 0x00A4.
0x00A4 Call hook to perform any chipset or OEM time dependent programming.
Things like programming wait states (DONE by IA64), shadow RAM cache-
ability (ALWAYS CACHEABLE).
Next, checkpoint 0x00A5.
0x00A5 Beep and set interrupt on.
Next, checkpoint 0x00A7.
0x00A7 Final OEM Patch called.
Prepare the final RUNTIME image in a segment for copying to F000 shad-
ow.
Test for the presence of INT 10 module in E000 segment.
Initialize the start and end offset variables to aid in the copying of the final
runtime segment.
Next, checkpoint 0x00AE.
0x00AE Uncompress DMI code and data modules.
Initialize SMBIOS header structure.
Pass control to DMI module for initialization.
Copy DMI code and data into final runtime image (F000).
Next, checkpoint 0x00AC.
0x00AC Building the multiprocessor table.
Next, checkpoint 0x00AB.
0x00AB Copy device present information to POST code segment.
Copy INT 13 to final runtime (F000).
If not enough room in F000, copy to E000.
Update pointers between Runtime and INT 13 interfaces.
Next, checkpoint 0x00AD.
0x00AD Prepare INT10 image.
Update the necessary data in different modules.
Update available space in SMBIOS data structure. BIOS POST complete.
Enable F000 writes to RAM (ALWAYS READ/WRITE), and go to checkpoint
0x00A8.