Bull NovaScale 5 5 Series, User Manual, Page: 324 / 384

C-10
User’s Guide
POST Codes Meaning
0x87EE Find PAL shadow size + align through SAL call.
0x87ED Find # of CPU’s present in the system, # of CPU, # of IOAPIC.
0x87EC Search for addition information EFI module (sal_efi_module_15) size,
align, and scratch buff size.
Initialize scratch buffer.
0x87EB Save maximum (PAL, EFI) shadow size and alignment.
Save PAL (ia32)/EFI shadow top address, size, alignment.
EFI module shadow base address (virtual/Physical), size, bottom address
(DATA+SAL+PAL+EFI).
Update virtual address entries in translation register descriptor, addresses
in MDT/
0x87EA Cache flush shadow.
0x87E9 PAL call for memory Test for SELF–TEST (pal_mem_for_test_25).
0x87E8 PAL call for PAL test (pal_test_proc_102) and save results.
0x87E7 PAL Call for pal_bus_get_features function # (pal_bus_get_features_09).
0x87E6 Set buslock mask=1 (non–atomic)
By PAL Call PAL Bus Set Feature (pal_bus_set_features_0a).
0x87E5 Set PMI entry point
PAL Call (pal_pmi_entrypoint_20).
0x87E4 PAL Cache Summary by PAL Call (pal_cache_summary_04).
0x87E3 PAL Cache Information set. PAL Call cache_info_02.
0x87E2 pal_mc_register_mem_1b/find CPU min state pointer.
Should be able now to initialize health, bsp/ap, cache size line size, sapic
ver, and cpuid.
Set minimal state save area,
BSPSTORE and SP.
0x87E1 Cache flush shadow.
0x87E0 Program IVA, ITR(0) for PAL, SAL runtime code & data area cr.iva/cr.ifa/cr.i-
tir/itr[r0].
0x87DF Clear semaphore and wait for all CPUs to synchronize.
0x87DE Sort CPU health. Already sorted for 2nd level BSP selection.
Store BSP/AP flag for respective CPU.
0x87DD Setup for interrupt wakeup reinitialization of BSPSTORE and SP if needed.
Wait for interrupt wakeup.
The low order quartets indicate the CPUs of the board which have com-
pleted the initialization
– Quartet =1 if the CPU has completed its initialization
– Quartet =0 if the CPU has not completed its initialization (for instance fail-
ure) or if it is CPU absent.
0x87DC Switch to virtual address Control register programming SET in PSR bn(44),
it(36), rt(27), dt(17), ic(13) .
Clear task priority register=cr.tpr.
Clear interruption function state register–cr.ifs.
Set legacy BIOS cs.base and ss.base.
Set es, ds, fs, gs=0 with 4G limit Legacy BIOS module (eip).
Give control at xxxx:e05b to IA–32 code.
Table 64. SAL–B POST codes