BitFlow NEO-PCE-CLB Hardware Reference Manual Download Page 183

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Camera Control Registers

CON22 Register

Version G.5

BitFlow, Inc.

NEO-8-85

8.25 CON22 Register

Bit

Name

FLASH_DATA

SCAN_STEP

Summary of Contents for NEO-PCE-CLB

Page 1: ...The Neon Hardware Reference Manual BitFlow Inc 400 West Cummings Park Suite 5050 Woburn MA 01801 USA Tel 781 932 2900 Fax 781 933 9965 Email support bitflow com Web www bitflow com Revision G 5 ...

Page 2: ...ppear in this document nor does it make a commit ment to update the information contained herein BitFlow Inc retains the right to make changes to these specifications at any time without notice All trademarks are properties of their respective holders Revision History Revision Date Comments F 0 2007 02 01 First Revision G 0 2008 04 25 Synchronized with SDK 5 00 G 1 2009 07 01 Synchronized with SDK...

Page 3: ...Thru Architecture NEO 2 2 Camera Specific Firmware for Camera Link Models CL Models Only NEO 2 7 Generation of Acquisition Windows NEO 2 9 The Horizontal Active Window HAW NEO 2 9 The Vertical Active Window VAW NEO 2 10 The Control Tables CTABs NEO 2 12 Vertical Control Table NEO 2 12 The VCTAB Functions NEO 2 13 Vertical Control Table Size NEO 2 15 Horizontal Control Table NEO 2 15 The HCTAB Func...

Page 4: ... Scan Step Mode NEO 4 2 Combining Modes NEO 4 2 Control Registers NEO 4 2 Observability NEO 4 3 Electrical Connections NEO 4 3 Understanding Stage Movement vs Quadrature Encoder Modes NEO 4 4 CON15 Register NEO 4 6 CON16 Register NEO 4 10 CON22 Register NEO 4 12 CON51 Register NEO 4 14 5 Encoder Divider Introduction NEO 5 1 Encoder Divider Details NEO 5 2 Formula NEO 5 2 Example NEO 5 2 Restrictio...

Page 5: ... 21 CON4 Register NEO 8 24 CON5 Register NEO 8 31 CON6 Register NEO 8 37 CON7 Register NEO 8 39 CON8 Register NEO 8 42 CON9 Register NEO 8 48 CON10 Register NEO 8 52 CON11 Register NEO 8 56 CON12 Register NEO 8 58 CON13 Register NEO 8 60 CON14 Register NEO 8 62 CON15 Register NEO 8 66 CON16 Register NEO 8 70 CON17 Register NEO 8 73 CON18 Register NEO 8 75 CON19 Register NEO 8 77 CON20 Register NEO...

Page 6: ... NEO 9 19 Destination Address NEO 9 20 Size of Transfer NEO 9 21 Next Quad Address NEO 9 22 10 Register and Memory Mapping Introduction NEO 10 1 Memory Types NEO 10 2 Registers NEO 10 2 UART NEO 10 2 DPM NEO 10 2 CTABs NEO 10 2 Memory Map NEO 10 3 Downloading Firmware NEO 10 5 PCI Configuration Space and Model Revision Information NEO 10 6 11 Electrical Interfacing Introduction NEO 11 1 Trigger NE...

Page 7: ...ches NEO 13 11 Switch S1 All Neon models NEO 13 11 Switch S2 NEO PCE CLB Revision 2 Only NEO 13 11 Switches S3 and S6 NEO PCE CLB Revision 2 Only NEO 13 11 Switches S4 and S7 NEO PCE CLB Revision 2 Only NEO 13 12 Switch S5 NEO PCE CLB Revision 2 Only NEO 13 12 The Camera Link Connector Pinouts CL1 to CL4 NEO 13 13 NEO PCE CLB Revision 1 I O Connector Standard Configuration P10 NEO 13 14 NEO PCE CL...

Page 8: ... TOC 6 BitFlow Inc Version ...

Page 9: ...eb site is www bitflow com Technical support is available at 781 932 2900 from 9 00 AM to 6 00 PM Eastern Stan dard Time Monday through Friday For technical support by email support bitflow com or by FAX 781 933 9965 please include the following Product name Camera type and mode being used Software revision number Computer CPU type PCI chipset bus speed Operating system Example code if applicable ...

Page 10: ...e used for numerical notation in this manual Table P 2 shows the numerical abbreviations that are used in this manual Table P 1 Base Abbreviations Base Designator Example Binary b 1010b Decimal None 4223 Hexidecimal h 12fah Table P 2 Numeric Abbreviations Abbreviation Value Example K 1024 256K M 1048576 1M ...

Page 11: ...his chapter is to explain at a block diagram level how the Neon fam ily works and what different versions are available There are a few models in the Neon family NEO PCE CLB supports one base CL cameras Revision 1 and Revision 2 NEO PCE CLD supports two base CL cameras NEO PCE CLQ supports four base CL cameras NEO PCE DIF supports one differential camera ...

Page 12: ...each block The Camera Link Interface block implements the CL base configuration This block has the Channel Link IC the Camera Control drivers and the serial communication trans ceivers The MUX block packs and assembles the data from the Camera Link block before it is pushed into the FIFO This block re arranges on the fly the data from the camera s taps so that the data is written in raster scan fo...

Page 13: ...and to external devices This block also handles start stop ping acquisition based on triggers and encoders The PCI interface block handles host reads writes to from the board These reads writes are used to program the board and to control its modes This block is also responsible for DMAing image data to the host memory or other devices The DMA engine uses chaining scatter gather DMA which can DMA ...

Page 14: ...ependent Virtual Frame Grabber VFG Put another way the NEO PCE CLD has two complete copies of the NEO PCE CLB as shown in Figure 1 1 The main difference being that both VFGs share a common I O connector P1 Each VFG can accept up to 24 bits at up to 85 Mhz pixel clock frequency The following paragraphs are a short description of each block CL Connector 2 UART PCI Device 1 PCI Device 0 Channel Link ...

Page 15: ... Control block handles both camera synchronization as well as external I O The block contains the CTABs which are uses to synchronize acquisition with the camera determine which pixels lines get acquired and which do not generate con trol signals to the camera and to external devices This block also handles start stop ping acquisition based on triggers and encoders The PCI interface block handles ...

Page 16: ...e NEO PCE CLQ has four complete copies of the NEO PCE CLB as shown in Figure 1 1 The main difference being that all VFGs share a common I O connector P1 Each VFG can accept up to 24 bits at up to 85 Mhz pixel clock frequency PCI Device 0 Acquisition and Control Logic CL Connector 1 UART Channel Link Chip CL1 PCI Device 1 Acquisition and Control Logic CL Connector 2 UART Channel Link Chip CL2 PCI D...

Page 17: ... dual ported memories The Camera Control block handles both camera synchronization as well as external I O The block contains the CTABs which are uses to synchronize acquisition with the camera determine which pixels lines get acquired and which do not generate con trol signals to the camera and to external devices This block also handles start stop ping acquisition based on triggers and encoders ...

Page 18: ...ription of each block The MUX block packs and assembles the data from the Camera Link block before it is pushed into the FIFO This block re arranges on the fly the data from the camera s taps so that the data is written in raster scan format in the host memory The FIFO block decouples the camera from the DMA engine It is implemented with dual ported memories 16 16 64 64 64 64 64 64 64 MUX Video Pi...

Page 19: ...cquisition based on triggers and encoders The PCI interface block handles host reads writes to from the board These reads writes are used to program the board and to control its modes This block is also responsible for DMAing image data to the host memory or other devices The DMA engine uses chaining scatter gather DMA which can DMA a virtually unlimited amount of data to memory without using any ...

Page 20: ...first board from BitFlow that supports the concept of the virtual frame grabber VFG The NEO PCE CLD and NEO PCE CLQ also use this con cept The idea behind the VFG is to separate the hardware platform connectors lam inate FPGAs etc from the frame grabbing functionality that software applications work with The primary reason behind this separation is that the turn around time for hardware is much lo...

Page 21: ... the slave VFG will also have to be configured for a two tap odd even pixel camera In all other ways however the two configurations do not have to match If you have a requirement where this rule must be broken please contact BitFlow s support department Custom combinations of firmware are available If there is a mismatch between the firmware required by one VFG s camera file and the firmware requi...

Page 22: ...Virtual vs Hardware Frame Grabbers The Neon NEO 1 12 BitFlow Inc Version G 5 ...

Page 23: ...tion Version G 5 BitFlow Inc NEO 2 1 Acquisition and Camera Control Chapter 2 2 1 Introduction This section covers acquisition and camera control for the R64 CL Karbon CL Neon CL Neon Dif Karbon CXP and the Alta AN families of frame grabbers ...

Page 24: ...in the data path which can delay the video by up to 8 clocks This is useful for accurate alignment of the video on the display The Video Selector selects the data source the video from the camera or the on board generated synthetic video The various patterns of synthetic video are useful mainly for the on board Built In Self Test BIST The Mask is a 32 bit mask replicated over the upper and lower 3...

Page 25: ...3 The amount of data written in the FIFOs is controlled by the Acquisition Window The vertical and horizontal size of this window is programmed in the ALPF and the ACLP registers respectively see Section 2 4 The timing of this window is determined by the camera and the acquisition state machine ...

Page 26: ...p Y Channel X Equalizer FIFO Channel Y Equalizer FIFO Channel Z Equalizer FIFO Camera Link Pixel Data Descrambler Synthetic Video VID_SOURCE PIX_DEPTH VIDEO_MASK CLIP FORMAT DISPLAY PIX_DEPTH SHIFT_RAW SHIFT_DSP SHIFT_RAW_LEFT SHIFT_DISP_LEFT SHIFT_DISP_SELECT Barrel Shifter Barrel Shifter Barrel Shifter Barrel Shifter 2 1 MUX 32 Bit Mask 32 Bit Mask Raster Scan Line Reformatter 8 Bit Clip 8 Bit C...

Page 27: ...D 2 Camera Link Pixel Data Descrambler Synthetic Video VID_SOURCE PIX_DEPTH VIDEO_MASK CLIP FORMAT DISPLAY PIX_DEPTH SHIFT_RAW SHIFT_DSP SHIFT_RAW_LEFT SHIFT_DISP_LEFT SHIFT_DISP_SELECT Barrel Shifter Barrel Shifter Barrel Shifter Barrel Shifter 2 1 MUX 32 Bit Mask 32 Bit Mask Raster Scan Line Reformatter 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip A to ...

Page 28: ...a Descrambler CoaXPress Data Packet Router Synthetic Video VID_SOURCE PIX_DEPTH VIDEO_MASK CLIP FORMAT DISPLAY PIX_DEPTH SHIFT_RAW SHIFT_DSP SHIFT_RAW_LEFT SHIFT_DISP_LEFT SHIFT_DISP_SELECT Barrel Shifter Barrel Shifter Barrel Shifter Barrel Shifter 2 1 MUX 32 Bit Mask 32 Bit Mask Raster Scan Line Reformatter 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip 8 Bit Clip ...

Page 29: ...or example the Neon which is Base Camera Link only will not support the MUX_8TS format as the is a Full Camera Link format Table 2 1 Firmware Options FORMAT Firmware Name Format Description 0 MUX 1 tap cameras 1 MUX_2TOEP 2 taps odd even pixels 2 MUX_2TOEL 2 taps odd even lines 3 MUX_2TS 2 taps segmented 4 MUX_2TS1RI 2 taps segmented right inverted 5 MUX_4TS 4 taps segmented 6 MUX_4T2S2RIOEP 4 tap...

Page 30: ...aps 8 way interleaved 21 MUX_BAY_2TS_RI Bayer decoder 2 taps segmented right inverted 22 MUX_4TS2RI Four taps segmented right two taps inverted 23 MUX_8TSOEP4RI Eight taps segments odd even pixel for right taps inverted 24 MUX_10WI Ten taps interleaved Table 2 1 Firmware Options FORMAT Firmware Name Format Description ...

Page 31: ... the ACPL is not a function of the bits per pixel The relationship between the number of pixels per line and the number of clocks per line is controlled by the firmware currently downloaded to the board The FORMAT register will indi cate which firmware is currently downloaded Each tap configuration requires a differ ent firmware file be downloaded The correct firmware is automatically downloaded b...

Page 32: ...d is pro grammed in CON17 The 17 bits define the maximum VAW as minimum 128K lines The total number of lines per frame that will be acquired can be different than the ALPF For a dual tap camera that supplies odd even lines for example the total num ber of lines acquired will be twice the ALPF as in the period of one HAW the camera supplies two lines The size of the VAW is on an arbitrary boundary ...

Page 33: ...on and Camera Control Generation of Acquisition Windows Version G 5 BitFlow Inc NEO 2 11 Figure 2 5 Generation of the Vertical Active Window VAW Vertical CTAB 2 1 MUX VAW Generator ALPF FEN VAW_START VSTART VAW ...

Page 34: ...rresponds to a different operation For example one bit might control the level of a signal going to the camera In this case the CTABs can be thought of as pro grammable waveform generators Another bit might cause an interrupt to occur on the PCI bus yet another bit might force the HCOUNT to go to zero The CTABs are fully programmable by software The details of the CTABs are described in this sec t...

Page 35: ...AB in ascending order The output of the VCTAB depends on the data that has been written in the VCTAB by the host If the VCOUNT is free running it will cyclically scan all the VCTAB s addresses Any arbitrary cyclic waveform can be implemented by programming the VCTAB with the adequate data The LOAD_V and RESET_V will enable the synchronization between external events and the waveforms generated by ...

Page 36: ...e first instance is when VCOUNT reaches 0000h the Stop at Zero case The other instance is when VCOUNT reaches 7FF0h the Vertical Stick case Stop at Zero Usually VCOUNT will reach zero because of a RESET_V signal After VCOUNT is reset there are programmable options defined by VCNT_RLS_ZERO Depending on this bitfield VCOUNT can continue to count or wait at zero till some event occurs usually the ass...

Page 37: ...ss VCOUNT will be loaded with the value 8000h by the rising falling edge of FEN if ENVLOAD is asserted FEN usually marks the start of a valid frame The start of the ver tical acquisition window can be placed starting at address 8000h ENVLOAD is a column in the VCTAB There are cameras that do not assert FEN Some other type of cameras assert only the start and stop of a frame In this case ENVLOAD ca...

Page 38: ...value of 2000h Logic for generating RESET_H the reset control signal to the HCOUNT When RESET_H is asserted HCOUNT is reset to 0 HCTAB a static memory SRAM that outputs eight HCTAB control signals The address of this SRAM is driven by HCOUNT Logic for generating CLOCK_H the clock to the HCOUNT This is a frequency divider CLOCK_H is PCLK the pixel clock divided by eight Note If RESET_H and LOAD_H a...

Page 39: ...hile the HAW is active HRESET will reset the HCOUNT ENHLOAD will allow the loading of the HCOUNT A location that has 1 will allow the loading of the HCOUNT A 0 will inhibit the loading of the HCOUNT GPH are general purpose horizontal functions See usage below The INC_H Control INC_H is the logic for incrementing HCOUNT There are only two instances when we want to inhibit the incrementing of HCTAB ...

Page 40: ... wait at address 0000h until ENCODER is asserted Horizontal Stick Using the previous example assume that after we asserted the sync signal to the cam era we expect the camera to give us a line i e assert LEN While we expect the cam era to assert LEN HCOUNT is still being incremented If it takes too long for the camera to respond HCOUNT will eventually reach and pass beyond 2000h A hori zontal acqu...

Page 41: ... s are four functions derived from the HCTAB and the VCTAB Those functions can define an arbitrary horizontal and or vertical waveform The definition of the CT s is given below CT 0 GPV 0 AND GPH 0 CT 1 GPV 1 AND GPH 1 CT 2 GPV 2 AND GPH 2 CT 3 GPV 3 AND GPH 3 Each CT has a vertical and a horizontal component Both components are pro grammed in the CTABs The minimum horizontal pulse is 8 PCLKs The ...

Page 42: ...The Control Tables CTABs The Neon NEO 2 20 BitFlow Inc Version G 5 2 5 6 Horizontal Control Table Size The Horizontal Control Table has 8000h 32 768 entries ...

Page 43: ...t be to begin acquiring pixels another might be to reset the VCOUNT back to zero Generally these state changes are caused by one or more events There are a number of events both horizontal and vertical that the board can react to These events are tied to operations by a set of programmable bitfields The details of these events are outlined in this section 2 6 1 Vertical Operations and Events The v...

Page 44: ...T Release From Zero This operation controls the behavior of VCOUNT when it reached zero See Table 2 7 Table 2 6 Vertical Events Event description Event Name TRIGGER asserted TRIG_ASRT TRIGGER de asserted TRIG_DASRT FEN asserted FEN_ASRT FEN de asserted FEN_DASRT TRIGGER is HI TRIG_HI TRIGGER is LO TRIG_LO RESET from VCTAB RST_VCTAB RESET from SW RST_SW Host writes acquisition command HOST_WCMD_GRA...

Page 45: ... stick point The pur pose of the stick point is to allow for very long periods of time between frames The stick point is located at 7ff0h See Table 2 9 Table 2 8 VCNT_RST Initiator VCNT_RST Comments End_of_VAW 0 Default operation reset at end of VAW TRIG_DASRT or End_ of_VAW 1 Triggered termination RST_VCTAB 2 Reset from VCTAB FEN asserted or 3 Reset from start of FEN TRIG_DASRT or RST_ VCTAB 4 Tr...

Page 46: ...us data mode which is not frame oriented In continuous data mode the board will acquire data based only on the clock and data qualifying signals There are no acquisition commands in this mode See Table 2 11 Note See also Section 2 7 for more details on the how the acquisition commands work Table 2 10 VCNT_LD Initiator VCNT_LD Comments None 0 No load FEN_ASRT and ENV LOAD 1 Assertion of FEN qualifi...

Page 47: ... 2 13 2 6 2 Horizontal Operations and Events The horizontal operations and events are related to the horizontal axis of an image in memory or on the display or line timing of a camera The operations are mainly commands to HCOUNT Each operation can be initiated by some event The selection of the event that will initiate the specific operation is done by a set of three control bits related to each o...

Page 48: ...nt from all of the others Table 2 14 Horizontal Operations Horizontal operation Control bits HCOUNT released from zero HCNT_RLS_ZERO HCOUNT reset to zero HCNT_RST HCOUNT load with 2000h HCNT_LD HCOUNT release from 1FF0h HCNT_RLS7F0 HCOUNT increment HCNT_INC Start horizontal active window HAW_START Table 2 15 Horizontal Events Event description Event Name ENCODER asserted ENC_ASRT ENCODER de assert...

Page 49: ...n it hits the stick point The pur pose of the stick point is to allow for very long periods of time between lines The stick point is located at 1ff0h See Table 2 18 Table 2 16 HCNT_RLS_ZERO Initiator HCNT_RLS_ ZERO Comments None 0 Normal operation mode no stop at zero ENC_ASRT 1 One shot mode wait for encoder for release Table 2 17 HCNT_RST Initiator HCNT_RST Comments END_OF_HAW 0 Default operatio...

Page 50: ...sion G 5 HCOUNT Load To 2000h This operation controls how and when HCOUNT loads jumps to 2000h see Table 2 19 Table 2 19 HCNT_LD Initiator HCNT_LD Comments None 0 No load LEN_ASRT 1 Load on LEN assert qualified with ENHLOAD column ENC_ASRT 2 Load on ENCODER assert qualified with ENHLOAD column ...

Page 51: ... the selected trigger ACQ_CON a bitfield that defines special acquisition modes for the state machine The current state of the machine can be observed by the AQCMD and AQSTAT bit fields described below 2 7 1 The Acquisition Bitfields The acquisition command bits AQCMD describe the command to be performed in the next frame The acquisition status bits AQSTAT describe the current command that is perf...

Page 52: ... a SNAP operation with ACQ_CON 1 In this mode after the TRIGGER has been asserted and the com mand executed the host must write a new command in the AQCMD field Figure 2 12 shows acquisition in ACQ_CON 2 mode Here as long as the GRAB command is on a frame will be acquired for every assertion of the TRIGGER In this mode there is no need for the host to write a new command Table 2 21 ACQ_CON ACQ_CON...

Page 53: ...nd Timing Figure 2 10 Abort Command Timing Grab command written AQSTAT set grabbing starts Freeze command written AQSTAT reset grabbing ends VACTIVE AQCMD 3 AQSTAT 3 0 0 0 0 VACTIVE AQCMD 3 AQSTAT 3 0 0 0 0 1 Grab command written AQSTAT set grabbing starts Abort command written AQCMD reset AQSTAT reset grabbing ends ...

Page 54: ...and and Status The Neon NEO 2 32 BitFlow Inc Version G 5 Figure 2 11 Snap Command Timing with ACQ_CON 2 Trigger asserts Snap command written AQCMD reset and AQSTAT set AQSTAT reset VACTIVE AQCMD 2 AQSTAT TRIG 2 0 0 0 0 ...

Page 55: ...cquisition Command and Status Version G 5 BitFlow Inc NEO 2 33 Figure 2 12 Grab Command Timing with ACQ_CON 2 Trigger asserts Grab command written AQSTAT set AQSTAT reset AQSTAT set AQSTAT reset VACTIVE AQCMD AQSTAT TRIG 2 2 0 0 0 3 3 ...

Page 56: ...L This section describes how the trigger circuit works The trigger is used to initiate a vertical operation for example capturing one frame There are three possible exter nal hardware inputs to the trigger circuit and a software input Assertion of the trigger can be delayed by up to 8192 lines granularity is 8 lines This delay works only with the external hardware trigger Figure 2 13 illustrates t...

Page 57: ...s Note The Alta does not have any encoder inputs This section describes how the encoder circuit works The encoder is used to initiate a horizontal operation for example capturing one line There are three possible exter nal hardware inputs to the encoder circuit and a software input The selected external encoder can be divided by the value in the ENC_DIV register Figure 2 14 illustrates the encoder...

Page 58: ...ignal Generator The Neon NEO 2 36 BitFlow Inc Version G 5 2 10 The On Board Signal Generator The on board signal generator has been replaced by the New Timing Generator NTG Please see Section 3 1 for more information ...

Page 59: ...the acquisi tion state machine the CTabs the VAW HAW or the camera connected The New Timing Generator supports both triggered and free running modes For trig gered modes it supports both the trigger signal for area cameras or the encoder sig nal for line cameras The NTG requires that the camera be put in one of two modes If the NTG is going to control just the line frame rate then the camera shoul...

Page 60: ...almost all applications Table 3 2 shows the resulting ranges The NTG uses a counter internally to create the programmed waveforms Because the NTG registers can be set for very long times reprogramming the NTG can be time consuming In order to speed up modifications to the NTG parameters the register NTG_RESET can be used Poke this bit to a 1 resets the NTG counter to zero and starts a new cycle wi...

Page 61: ...can be send to the CC lines on the CL connector or the GPOUT lines on the I O connector The CCx_CON bitfields can be used route the NTG signal to the CCs output For example program CC1_CON to 3 to get the NTG output on CC1 Similarly the GPOUTx_CON bitfields can be used to route the NTG signals to the GPOUTx outputs For example to put the NTG output on GPOUT1 program GPOUT1_CON to 6 The NTG wavefor...

Page 62: ... count up to NTG_EXPOSURE clocks then de assert the output It will then continue to count to NTG_EXPOSURE clocks then reset itself and start over In one shot mode the NTG clock will wait at zero and until the trigger is asserted it will then start counting On the first clock after the trigger is asserted it will assert its output It will then count up to NTG_EXPOSURE clocks then de assert its outp...

Page 63: ... 30 0 Free run mode 1 one shot mode waits for either the trigger or the encoder pules depending on NTR_TRIG_ MODE NTG_TRIG_MODE CON17 31 1 Encoder for NTG trigger 0 Trigger for NTG trigger NTG_INVERT CON18 30 0 NTG asserted high 1 NTG asserted low NTG_TIME_MODE CON18 31 0 Base NTG clock 1 Base NTG clock 128 see Table 3 1 for values NTG_EXPOSURE CON26 27 0 The exposure time in units of one NTG cloc...

Page 64: ...NTG Control Registers The Neon NEO 3 6 BitFlow Inc Version G 5 ...

Page 65: ...ward only stage movements The system can be be programmed to only acquire one line for each encoder count that corresponds to a physical location on the stage The encoder counter can be used in many different ways described in more details below 4 1 1 Simple Encoder Mode The most basic method of using a quadrature encoder is to use it like a standard sig nal phase encoder In this mode the quadratu...

Page 66: ... of the mechanical system vibrating jumping bouncing etc If these imperfections occur during the period of time where lines are being acquired the image will be distorted Lines on the object can be acquired more than once as the stage jitters To prevent re acquisition of lines a circuit has been added to the quadrature encoder system that can prevent any line from being acquired more than once To ...

Page 67: ...r that you wish to connect to For example if you want to connect a TLL A output to VFG 0 then you would use VFG0_ENCODER_TTL Table 4 1 Observability Registers Register Meaning QENC_COUNT Encoder counter QENC_PHASEA Phase of input A QENC_PHASEB Phase of input B QENC_DIR Direction of encoder QENC_INTRVL_IN Interval status QENC_NEW_LINES Indicates new lines are being acquired Table 4 2 TTL Quadrature...

Page 68: ...oder could be attached to any mechanical system however a back and forth stage is a simple way to illustrate these modes In Figure 4 1 you can see as the stage moves back and forth the encoder counts up and down Further in this example we assume QENC_AQ_DIR 1 which tells the sys tem to only acquire when the encoder counter is moving in the positive direction This is illustrated by solid lines in t...

Page 69: ...ure Encoder Modes Version G 5 BitFlow Inc NEO 4 5 Figure 4 2 shows all of the major quadrature encoder modes Figure 4 2 Quadrature Encoder Modes vs Acquisition Positive Negative Both Acquisition Direction Simple No Re Acquire Interval Not Valid Zoom In Mode ...

Page 70: ...L 8 QENC_INTRVL_LL 9 QENC_INTRVL_LL 10 QENC_INTRVL_LL 11 QENC_INTRVL_LL 12 QENC_INTRVL_LL 13 QENC_INTRVL_LL 14 QENC_INTRVL_LL 15 QENC_INTRVL_LL 16 QENC_INTRVL_LL 17 QENC_INTRVL_LL 18 QENC_INTRVL_LL 19 QENC_INTRVL_LL 20 QENC_INTRVL_LL 21 QENC_INTRVL_LL 22 QENC_INTRVL_LL 23 QENC_INTRVL_LL 24 QENC_DECODE 25 QENC_AQ_DIR 26 QENC_AQ_DIR 27 QENC_INTRVL_MODE 28 QENC_NO_REAQ 29 QENC_DUAL_PHASE 30 SCAN_STEP...

Page 71: ...red Whether lines are acquired as the counter incre ments through the interval or decrements through the interval or in both directions are controlled by QENC_AQ_DIR QENC_NO_ REAQ R W CON15 28 Karbon Neon This bit controls how the quadrature encoder system handles the situation where the encoder does not smoothly increase or decrease if QENC_AQ_DIR 1 If there is jitter in the encoder signal often ...

Page 72: ... a value or to what extremes the counter goes New lines will only be acquired when new values are reached Once the entire frame has been acquired the system must be reset The system can always be reset by poking QENC_RESET to 1 There are also ways that the system can automatically be reset see QENC_RESET_MODE QENC_DUAL_ PHASE R W CON15 29 Karbon Neon This bit controls which type of encoder is atta...

Page 73: ...Quadrature Encoder CON15 Register Version G 5 BitFlow Inc NEO 4 9 QENC_RESET WO CON15 31 Karbon Neon Poking this bit to a 1 resets the entire quadrate encoder system ...

Page 74: ...RVL_UL 7 QENC_INTRVL_UL 8 QENC_INTRVL_UL 9 QENC_INTRVL_UL 10 QENC_INTRVL_UL 11 QENC_INTRVL_UL 12 QENC_INTRVL_UL 13 QENC_INTRVL_UL 14 QENC_INTRVL_UL 15 QENC_INTRVL_UL 16 QENC_INTRVL_UL 17 QENC_INTRVL_UL 18 QENC_INTRVL_UL 19 QENC_INTRVL_UL 20 QENC_INTRVL_UL 21 QENC_INTRVL_UL 22 QENC_INTRVL_UL 23 QENC_INTRVL_UL 24 QENC_REAQ_MODE 25 QENC_REAQ_MODE 26 QENC_RESET_REAQ 27 N A 28 N A 29 N A 30 N A 31 N A ...

Page 75: ...ic modes do not require host interaction the reset will occur automatically when the specified conditions are met QENC_RESET_ REAQ WO CON16 26 Karbon Neon This register is used to reset the circuit that prevents the re acquisition of lines when QENC_NO_REAQ is set to 1 Writing a 1 to this register deletes the list of acquired lines thus next time the lines are passed over they will be acquired aga...

Page 76: ...ved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 SCAN_STEP 17 SCAN_STEP 18 SCAN_STEP 19 SCAN_STEP 20 SCAN_STEP 21 SCAN_STEP 22 SCAN_STEP 23 SCAN_STEP 24 SCAN_STEP 25 SCAN_STEP 26 SCAN_STEP 27 SCAN_STEP 28 SCAN_STEP 29 SCAN_STEP 30 SCAN_STEP 31 SCAN_STEP ...

Page 77: ...CAN_STEP R WO CON22 31 16 Karbon Neon This bitfield controls the number of encoder pulses that must occur before a trigger is issued to the system See SCAN_STEP_TRIG for more information The Scan Step cir cuit takes into account the interval and re acquisition functions ...

Page 78: ...T 6 QENC_COUNT 7 QENC_COUNT 8 QENC_COUNT 9 QENC_COUNT 10 QENC_COUNT 11 QENC_COUNT 12 QENC_COUNT 13 QENC_COUNT 14 QENC_COUNT 15 QENC_COUNT 16 QENC_COUNT 17 QENC_COUNT 18 QENC_COUNT 19 QENC_COUNT 20 QENC_COUNT 21 QENC_COUNT 22 QENC_COUNT 23 QENC_COUNT 24 QENC_PHASEA 25 QENC_PHASEB 26 QENC_DIR 27 QENC_INTRVL_IN 28 QENC_NEW_LINES 29 Reserved 30 Reserved 31 Reserved ...

Page 79: ... QENC_DIR RO CON51 26 Karbon Neon This bit displays the current quadrature encoder direction QENC_INTRVL_ IN RO CON51 27 Karbon Neon This bit indicates the current status of the quadrature encoder if the system is in inter val mode see QENC_INTRVL_MODE QENC_DIR Meaning 0 Direction is negative 1 Direction is positive QENC_INTRVL_IN Meaning 0 System is not inside the interval Encoder counter is not ...

Page 80: ...QENC_NO_REAQ 1 only lines that have not yet been scanned are acquired This bit can be used to determine of new lines are being traversed or if the system has backed up and is revisiting old lines QENC_NEW_LINES Meaning 0 The system is traversing lines that have already been visited If QENC_NO_REAQ 1 lines are not being acquired 1 The system is traversing new lines Lines are being acquired ...

Page 81: ... 03448 or 4 2666 Of course not all ration numbers in the available scaling range can be selected there are an infinite number of them However a useful selection of values is available which should support most applications The Encoder Divider circuit takes as its input the selected encoder input controlled by the register SELENC The output of the encoder divider drives the same parts of the board ...

Page 82: ... extremes and the scaling factors are not evenly distributed However a scaling factor can be generally found that meets the requirments of most applications 5 2 2 Example Let s assume that the encoder frequency Fin is 10 KHz and that we need an output Fout of 30 KHz This means that we need to multiply by 3 Set N 6 and M 21 This will a scaling factor of 3 048 The result is an effective line rate of...

Page 83: ... avoid this situation and handle encoder slow down stop gracefully the encoder divider has has limiting cir cuit that can be run in one of two different mode described in the following two sec tions Slow Tracking Mode ENC_DIC_FORCE_DC 0 In this mode when the input frequency goes below the minimum of 1 6 KHz the Encoder Divider circuit s output will continue to track the input but the output fre qu...

Page 84: ...ols the N factor the Encoder Divider equation ENC_DIV_FORCE_DC CON16 27 Controls the behavior when Fin falls below the minimum 0 Output runs in simple divider mode 1 Output goes to DC ENC_DIV_OPEN_LOOP CON16 28 Controls whether the output signal phase of the Encoder Divider is lock to the intput or is allowed to free run 0 Output phased locked to input 1 Ouput runs open loop ENC_DIV_FCLK_SEL CON16...

Page 85: ...le The PoCL standard is described in version 1 2 and later of the Camera Link Specifica tion The standard is available from the Automated Imaging Association Please see their web site for more information The PoCL standard is designed to be backwards compatible with existing equipment See Section Table 6 1 for more information The PoCL standard provides 12 volts of power at up to 0 5 amps Overcurr...

Page 86: ...quired No means the combination will not work and no images will be acquired but no damage will occur to any of the equipment Please see Section 6 3 for more information In summary the only way to use a PoCL camera is with a PoCL frame grabber and PoCL cable However with non PoCL cameras any combination will work Finally even if the particular combination does not work nothing will be damaged shou...

Page 87: ... applied Also if a power camera is removed the safe power system detects this situation and goes back to a non powered state Figure 6 1 shows the state of the PoCL safe power system It is important to understand the board powers up with the PoCL system turned off The PoCL system will not start up and no power will be applied to any connector until the register POCL_EN is set to 1 This is an extra ...

Page 88: ... POCL_EN 1 PoCL Power PoCL Camera Detected Wait for surge 0 5 S Wait for clock 3 0 S Check for clock No Clock Running PoCL Power Clock Detected No Clock PoCL GND Legacy Camera Cable POCL_EN 1 Check for clock No Clock Running PoCL GND Clock Detected No Clock EN_PO WER 0 Fuse Blows POCL_EN 0 Fuse Blows Wait for clock 3 0 S Fuse Blows ...

Page 89: ...indicates that the PoCL state machine waiting for the clock from the camera POCL_SENSE indicates that the PoCL state machine is looking to sense PoCL equipment POCL_CLK_DETECTED indicates that the clock has been detected coming back from the camera POCL_DETECTED indicates that the PoCL camera has been detected Only the register POCL_EN is a user programmable bit The other registers are useful for ...

Page 90: ...PoCL Control Registers The Neon NEO 6 6 BitFlow Inc Version G 5 ...

Page 91: ...ts Function and Relationship Register Details AQSTAT Acquisition status CON3 Section 8 6 FACTIVE Acquisition status vertical active CON3 Section 7 2 FCOUNT Acquisition status 3 bit frames counter CON3 Section 7 2 LCOUNT Camera status LEN is toggling CON4 Section 7 3 PCOUNT Camera status PCLK is toggling CON4 Section 7 3 FENCOUNT Camera status FEN is toggling CON4 Section 7 3 RD_TRIG_DIFF TTL OPTO ...

Page 92: ... both area scan and line scan comeras For both line scan and area scan cameras there is always a vertical size defined by ALPF FCOUNT is a 3 bit frame counter that is incremented by the rising edge of FACTIVE It can be used to track acquisition especially in triggered modes FCOUNT works for both area scan and line scan cameras ...

Page 93: ... a constant value from this register indicates that the camera s clock does not reach the acquisition cir cuitry LCOUNT is a 2 bit counter clocked by the camera s LEN Reading a constant value from this register indicates that the camera s LEN does not reach the acquisition cir cuitry FENCOUNT is a 2 bit counter clocked by the camera s FEN Reading a constant value from this register indicates that ...

Page 94: ...F TTL OPTO The Neon NEO 7 4 BitFlow Inc Version G 5 7 4 RD_TRIG_DIFF TTL OPTO RD_ENC_DIFF TTL OPTO The level of all trigger and encoder inputs can be read at any time This helps estab lish connection with external industrial equipment ...

Page 95: ...the current active state of the current selected trigger The trigger is selected by the SEL_TRIG register Each individual input can be monitored via the corresponding RD_TRIG_XXX bit but the TRIG_QUALIFIED always reports the state of the trigger input that is current being used by the acquisition circuitry ...

Page 96: ... and vertical CTABs VCOUNT is the address counter of the VCTAB This register indicates the cur rent VCTAB address HCOUNT is the 2 LSB of the HCTAB address counter This register indicates only if the HCTAB is cycling Reading a constant value on HCOUNT indicates that the HCTAB address is stuck LINES_TOGO specifies how more many lines there are till the end of the frame ...

Page 97: ...ideo from the first eight bits of the main con nector It is helpful to determine if the camera is reacting to light Covering the cam era s lens will yield a low value in this register Pointing the camera to a light source will yield a high value in this register Note This register is not available on all models ...

Page 98: ... BitFlow Inc Version G 5 7 8 DEST_ADD This register gives the DMA destination address During acquisition this register should change Reading a constant value from this register suggests that the DMA operation is not progressing ...

Page 99: ...uals you will see that almost all of these registers are the same There are only a few bits that are different between these two models these will be indicated in the bitfield definitions Registers that are related to DMA operations have their own chapters All of the registers are 32 bits wide These wide registers are named CON0 CON1 etc Each registers is broken into one or more bitfields Bitfield...

Page 100: ...ed with REG_ For example the bitfield CFREQ is referred to in software as REG_CFREQ Bitfield details This section describes how the bitfield is accessed The first part describes the how the bits can be accessed For exam ple R W means the register can be both read and writen See theTable 8 2 for details The second part is the wide reg ister that the bitfield is located in In the example above this ...

Page 101: ...d written RO Bitfield can only be read Writing to this bit has no effect WO Bitfield can only be written Reading from this bit will return meaningless values Karbon CL This bitfield is functional on the Karbon CL Karbon CXP This bitfield is functional on the Karbon CXP Neon This bitfield is functional on the Neon R64 This bitfield is functional on the R64 family Alta This bitfield is functional on...

Page 102: ... 4 CFGCLOCK 5 FW_7MHZ 6 Reserved 7 POCL_EN 8 CFREQ 9 CFREQ 10 CFREQ 11 Reserved 12 L_CLKCON 13 L_CLKCON 14 SEL_UCLKC_7MHZ 15 RELOAD_FPGA 16 FW_SEL 17 FW_SEL 18 FW_SEL 19 CPLD_MODE 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 103: ...e UART clock to 7 3 MHz If this bit is zero then the board has the original firmware and the UART can only be driver by an 8 MHz clock See also the bit SEL_ UCLK_7MHz POCL_EN R W CON0 7 Neon Karbon CXP On the Neon this bit turns the PoCL Safe Power system This bit must be set to one in order to enable power to PoCL cameras However the system uses the Safe Power system so a number of conditions mus...

Page 104: ... for test diagnostics SEL_UCLK_ 7MHZ R W CON0 14 Alta Karbon CL Neon R64 This bit selects the frequency that is used to driver the UART for serial communica tions This functionality is only available on boards with update firmware The bit FW_ 7MHZ can be used to check the version of the firmware CFREQ Frequency 0 000b DC 1 001b 3 75 MHz 2 010b 7 5 MHz 3 011b 15 MHz 4 100b 24 MHz 5 101b 30 MHz 6 11...

Page 105: ...pe of firmware For each major type of CCD tap configuration there is a separate firmware file that is down loaded to the board However in some cases different manufacturers chose slightly different ways to implement the same tap configuration In these cases this bitfield is used to select between the different modes As the meaning for this bitfield differ for each firmware file and these bits are ...

Page 106: ...T_RST 5 VCNT_RST 6 VCNT_LD 7 VCNT_LD 8 VCNT_LD 9 VCNT_RLS_STK 10 VCNT_RLS_STK 11 VCNT_RLS_STK 12 ABORT_CON 13 ABORT_CON 14 ABORT_CON 15 NO_VB_WAIT 16 ACQ_CON 17 ACQ_CON 18 ACQ_CON 19 FREEZE_CON 20 FREEZE_CON 21 FREEZE_CON 22 ACQ_SAFETY 23 NO_RULE 24 INT_CTAB 25 INT_OVSTEP 26 INT_HW 27 INT_TRIG 28 INT_SER 29 INT_QUAD 30 INT_TRIGCON 31 INT_TRIGCON ...

Page 107: ...edge of the trig ger 2 010b Level Mode VCOUNT sticks at zero only if the trig ger is de asserted If trigger is asserted then VCOUNT does not stick at zero VCOUNT is released from zero by the leading edge of trigger 3 011b Like mode 1 except FEN is the trigger 4 100b Like mode 2 except FEN is the trigger 5 101b One shot one time mode CTabs free run for AQ_ COUNT frames and then waits for the next t...

Page 108: ...bit has the following properties VCNT_LD Meaning 0 000b No load operation performed 1 001b VCOUNT is loaded at the assertion of FEN qualified with the ENVLOAD column in the VCTAB 2 010b VCOUNT is loaded at the assertion of FEN 3 011b VCOUNT is loaded at the assertion of trigger VCNT_RLS_STK Meaning 0 VCOUNT does not stick at 7FF0h 1 VCOUNT sticks at 7FF0h It will be released from that address by a...

Page 109: ...ork normally 2 010b While the GRAB command is on a frame will be acquired at the assertion of trigger 3 011b Continuous acquisition mode Host commands are ignored Data will be acquired continuously as long as the TRIGGER is asserted 4 100b A GRAB command will be issued every time the TRIGGER asserts The GRAB can be terminated after a programmable number of frames by using the AQ_ COUNT register Th...

Page 110: ...set if an overflow occurred in the FIFO or by the host writing to this bit The interrupt will be enabled if its corresponding mask ENINT_OVSTP has been set to 1 This interrupt can be cleared by the host writing a 0 to this location For the host to be able to write to this location the CMDWRITE code must be set to 2 INT_HW R W CON1 26 Alta Karbon CL Karbon CXP Neon R64 This interrupt will be set by...

Page 111: ...implements the serial communi cation protocol The interrupt will be enabled if its corresponding mask ENINT_SER has been set to 1 This interrupt can be cleared by the host writing to the UART INT_QUAD R W CON1 29 Alta Karbon CL Karbon CXP Neon R64 This interrupt will be set by a DMA QUAD or by the host writing to this bit The inter rupt will be enabled if its corresponding mask ENINT_QUAD has been...

Page 112: ...Karbon CXP Neon R64 This register controls the trigger edge that will cause an interrupt INT_TRIGCON Meaning 0 00b reserved 1 01b Assert interrupt on rising edge of trigger 2 10b Assert interrupt on falling edge of trigger 3 11b Assert interrupt on both the rising and the falling edge of the trigger ...

Page 113: ...RO 3 HCNT_RST 4 HCNT_RST 5 HCNT_RST 6 HCNT_LD 7 HCNT_LD 8 HCNT_LD 9 HCNT_RLS_STK 10 HCNT_RLS_STK 11 HCNT_RLS_STK 12 RST_HVCOUNT 13 RST_DPM_ADDR 14 CTABHOLD 15 Reserved 16 CC1_CON 17 CC1_CON 18 CC1_CON 19 CC2_CON 20 CC2_CON 21 CC2_CON 22 CC3_CON 23 CC3_CON 24 CC3_CON 25 CC4_CON 26 CC4_CON 27 CC4_CON 28 CMDWRITE 29 CMDWRITE 30 CMDWRITE 31 QTBSRC ...

Page 114: ... register controls the loading of the HCOUNT with 2000h HCNT_RLS_ZERO Meaning 0 HCOUNT does not stop at 000h 1 HCOUNT stops at 000h It will be released by the assertion of the encoder HCNT_RST Meaning 0 000b HCOUNT will be reset by the end of the Horizontal Active Window 1 001b HCOUNT will be reset by the assertion of FEN or the HRESET from the HCTAB 2 010b HCOUNT will be reset by the HRESET in th...

Page 115: ...CL Karbon CXP Neon R64 This bit has the following properties CTABHOLD R W CON2 14 Alta Karbon CL Karbon CXP Neon R64 This bit has the following properties HCNT_RLS_STK Meaning 0 HCOUNT will not stick at 1FF0h 1 HCOUNT will stick at 1FF0h It will be released by a load or reset command RST_HVCOUNT Meaning 0 Normal operation for HCOUNT VCOUNT 1 Reset HCOUNT VCOUNT RST_DPM_ADDR Meaning 0 Normal operat...

Page 116: ...elects the signal steered to the CC2 CC1_CON Signal steered to CC1 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running signal generated on board 4 100b Trigger input 5 101b GPIN0 6 110b 0 7 111b 1 CC2_CON Signal steered to CC2 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running signal generated on board 4 100b Trigger Input 5 101b GPIN0...

Page 117: ...ly different than the previous three CC4 can be controlled by CT3 This changes allows all four CTs to be tied to a CC CC3_CON Signal steered to CC3 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running signal generated on board 4 100b Trigger input 5 101b GPIN0 6 110b 0 7 111b 1 CC4_CON Signal steered to CC4 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTA...

Page 118: ...hat interrupt can not be asserted by its source It can be modified only by the host This mechanism allows to perform reliable read modify write cycles QTBSRC RO CON2 31 Alta Karbon CL Karbon CXP Neon R64 Always read back 1 CMDWRITE Interrupt allowed for host access 0 000b No interrupt can be accessed by host 1 001b INT_CTAB 2 010b INT_OVSTP 3 011b INT_HW 4 100b INT_TRIG 5 101b INT_QTAB 6 110b INT_...

Page 119: ... 1 AQCMD 2 AQSTAT 3 AQSTAT 4 FACTIVE 5 FCOUNT 6 FCOUNT 7 FCOUNT 8 REV_DCC 9 REV_DCC 10 REV_DCC 11 REV_DCC 12 REV_DCC 13 REV_DCC 14 REV_DCC 15 REV_DCC 16 REV_DCC 17 REV_DCC 18 REV_DCC 19 REV_DCC 20 REV_DCC 21 REV_DCC 22 REV_DCC 23 REV_DCC 24 AUX_DETECT 25 GPIN0 26 GPIN1 27 GPIN2 28 GPIN3 29 GPIN4 30 SW 31 SW ...

Page 120: ...lta Karbon CL Karbon CXP Neon R64 FCOUNT RO CON3 7 5 Alta Karbon CL Karbon CXP Neon R64 This is a 3 bit modulo 8 counter The counter is incremented by the start of the Verti cal Acquisition Window It is used as a debug diagnostic tool REV_DCC WO CON3 23 8 Alta Karbon CL Karbon CXP Neon R64 FW revision AQCMD Meaning 0 00b FREEZE 1 01b ABORT 2 10b SNAP 3 11b GRAB AQSTAT Meaning 0 00b FREEZE 1 01b AB...

Page 121: ...on 11 4 for interfacing information GPIN2 RO CON3 27 Alta Karbon CL Neon R64 Controlled by inputs on the IO connector The logical value applied to the corre sponding pin will be reflected in this register See also Section 11 4 for interfacing information GPIN3 RO CON3 28 Alta Karbon CL Neon R64 Controlled by inputs on the IO connector The logical value applied to the corre sponding pin will be ref...

Page 122: ...W 3 ENINT_TRIG 4 ENINT_SER 5 ENINT_QUAD 6 EOF_IN_AQ 7 INT_ANY 8 ENINT_ALL 9 AUX_CAM 10 GPOUT0 11 GPOUT1 12 GPOUT2 13 GPOUT3 14 GPOUT4 15 GPOUT5 16 GPOUT6 17 RST_SER 18 OVS 19 RST_OVS 20 CL_DISABLE 21 LCOUNT 22 LCOUNT 23 PCOUNT 24 PCOUNT 25 FENCOUNT 26 FENCOUNT 27 POP_TOSS 28 PUMP_OFF 29 DMA_BUSY 30 HAW_START 31 VAW_START ...

Page 123: ...HW R W CON4 2 Alta Karbon CL Karbon CXP Neon R64 This bit has the following properties ENINT_TRIG R W CON4 3 Alta Karbon CL Karbon CXP Neon R64 This bit has the following properties ENINT_CTAB Meaning 0 CTAB interrupt disabled 1 CATB interrupt enabled ENINT_OVSTEP Meaning 0 OVERSTEP interrupt disabled 1 OVERSTEP interrupt enabled ENINT_HW Meaning 0 HW interrupt disabled 1 HW interrupt enabled ENIN...

Page 124: ...ts out of the queue before starting acquisition With this functionality enable interrupts only occur during acquisition INT_ANY RO CON4 7 Alta Karbon Neon On the products that use the PLDA engine this bit indicates that an interrupt was emitted by the board This bit can be checked first to see if some event caused the interrupt before inquiring other bits to see the actual cause of the interrupt E...

Page 125: ...POUTs and Section 11 5 for electrical interfacing GPOUT3 R W CON4 13 Alta Karbon CL Neon R64 The value written in this register will be reflected on the IO connector See also CON8 for signals steered to the GPOUTs and Section 11 5 for electrical interfacing GPOUT4 R W CON4 14 Alta Karbon CL Neon R64 The value written in this register will be reflected on the IO connector See also CON8 for signals ...

Page 126: ...sed for diagnostics For normal operation this bit should always be set to 0 For CXP board bit enables disables the clock coming from the CXP engine used for diagnostics For normal operation this bit should always be set to 0 RST_SER Meaning 0 UART normal operation 1 UART s reset line asserted OVS Meaning 0 No overstep occurred since this bit was cleared 1 At least one overstep occurred since this ...

Page 127: ...ctive PCLK FENCOUNT RO CON4 26 25 Alta Karbon CL Karbon CXP Neon R64 This is a 2 bit counter clocked by the FEN supplied by the Camera Link main connec tor Reading this counter and observing changes between reads indicates an active FEN POP_TOSS R W CON4 27 R64 Alta Karbon CL Karbon CXP Neon R64 For normal operation this bit should be set to 0 It is used for high level clean up PUMP_OFF R W CON4 2...

Page 128: ...n R64 This bit has the following properties DMA_BUYS Meaning 0 DMA engine is idle 1 DMA engine is currently DMAing data HAW_START Meaning 0 The start of the Horizontal Active Window HAW is controlled by the start of the LEN 1 The start of the Horizontal Active Window is con trolled by the HSTART column in the HCTAB VAW_START Meaning 0 The start of the Vertical Active Window VAW is con trolled by t...

Page 129: ...CPOL 7 SW_ENC 8 RD_TRIG_DIFF 9 RD_TRIG_TTL 10 RD_TRIG_OPTO 11 RD_ENC_DIFF 12 RD_ENC_TTL 13 RD_ENC_OPTO 14 TRIGGER_DELAY 15 TRIGGER_DELAY 16 TRIGGER_DELAY 17 TRIGGER_DELAY 18 TRIGGER_DELAY 19 TRIGGER_DELAY 20 TRIGGER_DELAY 21 TRIGGER_DELAY 22 TRIGGER_DELAY 23 TRIGGER_DELAY 24 ENINT_EOF 25 INT_EOF 26 RD_FEN 27 CCSYNC 28 CCSYNC 29 CCSYNC 30 EN_TRIGGER 31 EN_ENCODER ...

Page 130: ... the SW trigger SEL_TRIG Meaning 0 00b The trigger used by the board is the differential trig ger on the IO connector 1 01b The trigger used by the board is the TTL trigger on the IO connector 2 10b The trigger used by the board is the opto coupled trigger on the IO connector 3 11b The FEN signal on the CL1 connector will be used as trigger When this mode is used the register FEN POL is used to co...

Page 131: ...L Neon R64 This register reflects the status of the differential trigger input on the IO connector pins 1 2 RD_TRIG_TTL RO CON5 9 Alta Karbon CL Neon R64 This register reflects the status of the TTL trigger input on the IO connector pin 3 SELENC Meaning 0 00b The encoder used by the board is the differential encoder on the IO connector 1 01b The encoder used by the board is the TTL encoder on the ...

Page 132: ...coupled encoder input on the IO connec tor pins 10 11 TRIGGER_DELAY R W CON5 23 14 Alta Karbon CL Karbon CXP Neon R64 The number N written in this register will delay the trigger by 8N lines ENINT_EOF R W CON4 24 Alta Karbon CL Karbon CXP Neon R64 This bitfield has the following properties INT_EOF R W CON4 25 Alta Karbon CL Karbon CXP Neon R64 This interrupt will be set by the acquisition state ma...

Page 133: ...bon CL Neon R64 This bitfield has the following properties INT_TRIG Meaning 0 No interrupt from end of frame 1 Interrupt from end of frame CCSYNC Meaning 0 000b CCs are not synchronized 1 001b CCs are synchronized to the pixel clock of the pri mary camera 2 010b CCs are synchronized to the pixel clock of the sec ondary camera 3 011b Each set of CCs are synchronized to the pixel clock of their corr...

Page 134: ...EO 8 36 BitFlow Inc Version G 5 EN_ENCODER R W CON5 31 Alta Karbon CL Neon R64 This bitfield has the following properties EN_ENCODER Meaning 0 External HW selected encoder is disabled 1 External HW selected encoder is enabled ...

Page 135: ...7 VCOUNT 8 VCOUNT 9 VCOUNT 10 VCOUNT 11 VCOUNT 12 VCOUNT 13 VCOUNT 14 VCOUNT 15 VCOUNT 16 VCOUNT 17 LAL 18 ENC_DIV ENC_DIV_M 19 ENC_DIV ENC_DIV_M 20 ENC_DIV ENC_DIV_M 21 ENC_DIV ENC_DIV_M 22 ENC_DIV ENC_DIV_M 23 ENC_DIV ENC_DIV_M 24 ENC_DIV ENC_DIV_M 25 ENC_DIV ENC_DIV_M 26 ENC_DIV ENC_DIV_M 27 ENC_DIV ENC_DIV_M 28 HCOUNT 29 HCOUNT 30 TRIG_QUALIFIED 31 Reserved ...

Page 136: ...the board Programming this register to 0 or 1 will both divide by 1 ENC_DIV_M R W CON6 27 18 Karbon CL Karbon CXP Neon R64 This register represents the M parameter of the encoder divider equation See Sec tion 5 1 for more information HCOUNT R W CON6 29 28 Alta Karbon CL Karbon CXP Neon R64 This register reflects the current value of the two LSBs of the HCOUNT Reading this register and observing ch...

Page 137: ... 4 AQ_COUNT 5 AQ_COUNT 6 AQ_COUNT 7 AQ_COUNT 8 AQ_COUNT 9 AQ_COUNT 10 AQ_COUNT 11 AQ_COUNT 12 AQ_COUNT 13 AQ_COUNT 14 AQ_COUNT 15 AQ_COUNT 16 AQ_COUNT 17 AQ_COUNT 18 AQ_COUNT 19 AQ_COUNT 20 SEL_REG_GEN 21 SEL_REG_GEN 22 GEN_ONESHOT 23 Reserved 24 TAG_BANK 25 TAG_BANK 26 TAG_BANK 27 TAG_BANK 28 TAG_BANK 29 TAG_BANK 30 NTG_TO_ENC 31 NTG_TO_TRIG ...

Page 138: ...s bit controls the mode of the special signal generator available in the TVI camera specific firmware TAG_BANK RO CON7 29 24 R64 This is the calculated bank from the address generator latched by the TAG QUAD diagnostics test register NTG_TO_ENC R W CON7 30 Karbon CL Karbon CXP Neon This bit provides the ability for the NTG timing generator to rung the encoder input directly This bit overrides the ...

Page 139: ...CL Karbon CXP Neon This bit provides the ability for the NTG timing generator to rung the trigger input directly This bit overrides the selection made by the SEL_TRIG bit NTG_TO_TRIG Meaning 0 The trigger circuit is driven by the selected external trigger source 1 The trigger circuit is driven by the NTG ...

Page 140: ...UT1_CON 6 GPOUT2_CON 7 GPOUT2_CON 8 GPOUT2_CON 9 GPOUT3_CON 10 GPOUT3_CON 11 GPOUT3_CON 12 GPOUT4_CON 13 GPOUT4_CON 14 GPOUT4_CON 15 GPOUT5_CON 16 GPOUT5_CON 17 GPOUT5_CON 18 GPOUT6_CON 19 GPOUT6_CON 20 GPOUT6_CON 21 AFPDF 22 AFPDF 23 Reserved 24 RLE_LOAD_H 25 RLE_LOAD_H 26 RLE_LOAD_H 27 RLE_LOAD_H 28 RLE_LOAD_V 29 RLE_LOAD_V 30 RLE_LOAD_V 31 RLE_LOAD_V ...

Page 141: ...T2 from CTAB 4 100b CT3 from CTAB 5 101b Internally generated CLOCK frequency controlled by CFREQ in CON1 6 110b Internally generated signal frequency and duty cycle controlled by CON17 7 111b The encoder input signal is routed to the GPOUT0 output signal GPOUT1_CON Selected signal steered to GPOUT1 0 000b GPOUT1 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from...

Page 142: ...01b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTAB 4 100b CT3 from CTAB 5 101b Internally generated CLOCK frequency controlled by CFREQ in CON1 6 110b Internally generated signal frequency and duty cycle controlled by CON17 7 111b reserved GPOUT3_CON Selected signal steered to GPOUT3 0 000b GPOUT3 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTAB 4...

Page 143: ... CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTAB 4 100b CT3 from CTAB 5 101b Internally generated CLOCK frequency controlled by CFREQ in CON1 6 110b Internally generated signal frequency and duty cycle controlled by CON17 7 111b reserved GPOUT5_CON Selected signal steered to GPOUT5 0 000b GPOUT5 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 fr...

Page 144: ... LEN signal is asserted The units of value in this bit field is RLE entry not the CTAB location In other words if the jump point is 0x8000 CTAB location but the RLE entry for this location is 3 then this register should be pro grammed to 3 GPOUT6_CON Selected signal steered to GPOUT6 0 000b GPOUT6 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTAB 4 100b CT3...

Page 145: ...at use RLE CTabs this register controls the location that the vertical RLE counter jumps to when the FEN signal is asserted The units of value in this bitfield is RLE entry not the CTAB location In other words if the jump point is 0x20000 CTAB location but the RLE entry for this location is 3 then this register should be pro grammed to 3 ...

Page 146: ...MUX_REV 4 MUX_REV 5 MUX_REV 6 MUX_REV 7 MUX_REV 8 MUX_REV 9 MUX_REV 10 MUX_REV 11 MUX_REV 12 TRIM 13 TRIM 14 TRIM 15 TRIM 16 FW_TYPE 17 FW_TYPE 18 FW_TYPE 19 FW_TYPE 20 DISPLAY 21 CLIP 22 SHORT_FRAME 23 RST_CALC_BANK 24 CALC_BANK 25 CALC_BANK 26 CALC_BANK 27 CALC_BANK 28 CALC_BANK 29 CALC_BANK 30 ACPL_MUL 31 ACPL_MUL ...

Page 147: ... field has the opposite effect of the DELAY field in CON14 FW_TYPE RO CON9 19 16 Alta Karbon CL Karbon CXP Neon R64 Firmware type DISPLAY R W CON9 20 Alta Karbon CL Karbon CXP Neon R64 This bit controls the acquisition of data that is more than 8 bits pixel When this bit is set only the 8 LSB of the data will be acquired in each lane To be able to display the 8 MSB or any other consecutive group o...

Page 148: ... VGA monitors set in 256 colors mode The upper and lower 15 gray levels are dedicated to Windows graphics SHORT_FRAME R W CON9 22 Alta Karbon CL Karbon CXP Neon R64 Future use RST_CALC_ BANK R W CON9 23 Alta Karbon CL Karbon CXP Neon R64 For normal operation this bit should be 0 CALC_BANK RO CON9 29 24 Alta Karbon CL Karbon CXP Neon R64 Value of the current calculated starting bank DISPLAY Meaning...

Page 149: ...Karbon CL Karbon CXP Neon R64 This register is used to increase the maximum line size the board can acquire The set tings act as multiplier for the ACPL Active Clocks Per Line register ACPL_MUL Meaning 0 00b Normal operation ACPL is used as is 1 01b ACPL is multiplied by 2 2 10b Reserved 3 11b Reserved ...

Page 150: ...PL 2 ACPL 3 ACPL 4 ACPL 5 ACPL 6 ACPL 7 ACPL 8 ACPL 9 ACPL 10 ACPL 11 ACPL 12 ACPL 13 ACPL 14 ACPL 15 ACPL 16 ACPL 17 FORMAT 18 FORMAT 19 FORMAT 20 FORMAT 21 FORMAT 22 VID_SOURCE 23 VID_SOURCE 24 VID_SOURCE 25 VID_SOURCE 26 PIX_DEPTH 27 PIX_DEPTH 28 PIX_DEPTH 29 PIX_DEPTH 30 PIX_DEPTH 31 FORCE_8BIT ...

Page 151: ...e Format Description 0 00000b MUX 1 tap cameras 1 00001b MUX_2TOEP 2 taps odd even pixels 2 00010b MUX_2TOEL 2 taps odd even lines 3 00011b MUX_2TS 2 taps segmented 4 00100b MUX_2TS1RI 2 taps segmented right inverted 5 00101b MUX_4TS 4 taps segmented 6 00110b MUX_4T2S2RIOEP 4 taps odd even pixels right taps inverted 7 00111b MUX_4TQ2RI2BU 4 quads right quads inverted bottom quads upside down 8 010...

Page 152: ...egmented right two taps inverted 23 10111b MUX_8TSOEP4RI Eight taps segments odd even pixel for right taps inverted 24 11000b MUX_10WI Ten taps interleaved FORMAT Firmware Name Format Description VID_SOURCE Video source 0 0000b Camera 1 0001b Camera special mode for cameras that do not assert the VALID signal 2 0010b reserved 3 0011b Synthetic horizontal static wedge 4 0100b Synthetic dynamic wedg...

Page 153: ...its 3 0011b 14 bits 4 0100b 16 bits 5 0101b 3x8 bits BGR DMAed as 32 bits upper MSB set to 00h 6 0110b 3x8 bits BGR DMAed as 24 bits packed 7 0111b 3x10 bits RGB DMAed as 32 bits display mode is 24 bits 8 1000b 3x12 bits RGB DMAed as 48 bits packed display mode is 24 bits 9 1001b 32 bits 10 1010b 64 bits 11 1011b 3x8 bits RGB DMAed as 32 bits upper MSB set to 00h 12 1100b 3x8 bits RGB DMAed as 24 ...

Page 154: ...D 5 ALAST_ADD 6 ALAST_ADD 7 ALAST_ADD 8 ALAST_ADD 9 ALAST_ADD 10 ALAST_ADD 11 ALAST_ADD 12 ALAST_ADD 13 ALAST_ADD 14 ALAST_ADD 15 DPM_WP 16 BLAST_ADD 17 BLAST_ADD 18 BLAST_ADD 19 BLAST_ADD 20 BLAST_ADD 21 BLAST_ADD 22 BLAST_ADD 23 BLAST_ADD 24 BLAST_ADD 25 BLAST_ADD 26 BLAST_ADD 27 BLAST_ADD 28 BLAST_ADD 29 BLAST_ADD 30 BLAST_ADD 31 UART_MASTER ...

Page 155: ...11 15 Alta Karbon CL Karbon CXP Neon R64 Prevents the DPM memory from be written by the acquisition engine Should normally be set to 0 BLAST_ADD RO CON11 30 16 Alta Karbon CL Karbon CXP Neon R64 Last address for lane B used for diagnostics UART_MASTER R W CON11 31 Karbon CL This bit controls which Karbon VFG is in control of the UART Poke this bit to one in order to take control of the UART ...

Page 156: ...DD 5 CLAST_ADD 6 CLAST_ADD 7 CLAST_ADD 8 CLAST_ADD 9 CLAST_ADD 10 CLAST_ADD 11 CLAST_ADD 12 CLAST_ADD 13 CLAST_ADD 14 CLAST_ADD 15 Reserved 16 DLAST_ADD 17 DLAST_ADD 18 DLAST_ADD 19 DLAST_ADD 20 DLAST_ADD 21 DLAST_ADD 22 DLAST_ADD 23 DLAST_ADD 24 DLAST_ADD 25 DLAST_ADD 26 DLAST_ADD 27 DLAST_ADD 28 DLAST_ADD 29 DLAST_ADD 30 DLAST_ADD 31 RGBHSI ...

Page 157: ...t address for lane C used for diagnostics DLAST_ADD R W CON11 30 16 Alta Karbon CL Karbon CXP Neon R64 Last address for lane D used for diagnostics RGBHSI R W CON11 31 Alta On boards that can do real time color conversion from RGB to HSI color space the board controls what color space is put out RGBHSI Meaning 0 Output RGB 1 Output HSI ...

Page 158: ...SK 6 VIDEO_MASK 7 VIDEO_MASK 8 VIDEO_MASK 9 VIDEO_MASK 10 VIDEO_MASK 11 VIDEO_MASK 12 VIDEO_MASK 13 VIDEO_MASK 14 VIDEO_MASK 15 VIDEO_MASK 16 VIDEO_MASK 17 VIDEO_MASK 18 VIDEO_MASK 19 VIDEO_MASK 20 VIDEO_MASK 21 VIDEO_MASK 22 VIDEO_MASK 23 VIDEO_MASK 24 VIDEO_MASK 25 VIDEO_MASK 26 VIDEO_MASK 27 VIDEO_MASK 28 VIDEO_MASK 29 VIDEO_MASK 30 VIDEO_MASK 31 VIDEO_MASK ...

Page 159: ...61 VIDEO_MASK R W CON13 31 0 Alta Karbon CL Karbon CXP Neon R64 With the aid of this mask individual bits in the video data stream can be set to 0 The 32 bit mask is duplicated for the 32 MSB of a 64 bit word Bit N in VIDEO_MASK Meaning 0 Set bit N to 0 1 Pass bit N as is ...

Page 160: ...ONS 4 BUTTONS 5 BUTTONS 6 BUTTONS 7 BUTTONS 8 BUTTONS 9 BUTTONS 10 BUTTONS 11 BUTTONS 12 BUTTONS 13 BUTTONS 14 BUTTONS 15 BUTTONS 16 SHIFT_RAW 17 SHIFT_RAW 18 SHIFT_RAW 19 SHIFT_RAW 20 SHIFT_RAW_LEFT 21 DELAY 22 DELAY 23 DELAY 24 SWAP 25 UART_CON 26 UART_CON 27 Reserved 28 DPM_SPLIT 29 DPM_SPLIT 30 DPM_SPLIT 31 DPM_SPLIT ...

Page 161: ... Neon R64 This bitfield has the following properties BUTTONS R W CON14 15 3 Alta Karbon CL Karbon CXP Neon R64 R W register for test diagnostics SHIFT_RAW R W CON14 19 16 Alta Karbon CL Karbon CXP Neon R64 This register defines for the barrel shifter the amount of shift for the data to be acquired SW_RESET Meaning 0 Reset de asserted 1 General reset to acquisition circuitry FENPOL Meaning 0 FEN is...

Page 162: ...he CTABs is 8 clocks so both DELAY and the CTABS may have to be used in together to accommodate for some delays The net effect for a simple one tap camera will be a shifting to the right of the dis played image For multi tap cameras the visual effect is more complex and depends on the taps architecture All taps are delayed by the same amount The purpose of this bit field is to align the image pres...

Page 163: ..._SPLIT R W CON14 31 28 Alta Karbon CL Karbon CXP Neon R64 This register controls how incoming data is written to the DPM DPM_SPLIT Mode 0 0000b Normal mode 1 0001b Each tap s output is split in half 2 0010b to 14 1110b Reserved 15 1111b Each tap s output is written in 4K chunks ...

Page 164: ...LL 8 QENC_INTRVL_LL 9 QENC_INTRVL_LL 10 QENC_INTRVL_LL 11 QENC_INTRVL_LL 12 QENC_INTRVL_LL 13 QENC_INTRVL_LL 14 QENC_INTRVL_LL 15 QENC_INTRVL_LL 16 QENC_INTRVL_LL 17 QENC_INTRVL_LL 18 QENC_INTRVL_LL 19 QENC_INTRVL_LL 20 QENC_INTRVL_LL 21 QENC_INTRVL_LL 22 QENC_INTRVL_LL 23 QENC_INTRVL_LL 24 QENC_DECODE 25 QENC_AQ_DIR 26 QENC_AQ_DIR 27 QENC_INTRVL_MODE 28 QENC_NO_REAQ 29 QENC_DUAL_PHASE 30 SCAN_STE...

Page 165: ...range lines are not acquired Whether lines are acquired as the counter increments through the interval or decrements through the interval or in both directions is con trolled by QENC_AQ_DIR QENC_NO_ REAQ R W CON15 28 Karbon CL Karbon CXP Neon This bit controls how the quadrature encoder system handles the situation where the encoder does not smoothly increase or decrease if QENC_AQ_DIR 1 If there ...

Page 166: ...o what extremes the counter goes New lines will only be acquired when new values are reached Once the entire frame has been acquired the system must be reset The system can always be reset by poking QENC_RESET to 1 There are also ways that the system can automatically be reset see QENC_RESET_MODE QENC_DUAL_ PHASE R W CON15 29 Karbon CL Karbon CXP Neon This bit controls which type of encoder is att...

Page 167: ...Camera Control Registers CON15 Register Version G 5 BitFlow Inc NEO 8 69 QENC_RESET WO CON15 31 Karbon CL Karbon CXP Neon Poking this bit to a 1 resets the entire quadrate encoder system ...

Page 168: ...TRVL_UL 9 QENC_INTRVL_UL 10 QENC_INTRVL_UL 11 QENC_INTRVL_UL 12 QENC_INTRVL_UL 13 QENC_INTRVL_UL 14 QENC_INTRVL_UL 15 QENC_INTRVL_UL 16 QENC_INTRVL_UL 17 QENC_INTRVL_UL 18 QENC_INTRVL_UL 19 QENC_INTRVL_UL 20 QENC_INTRVL_UL 21 QENC_INTRVL_UL 22 QENC_INTRVL_UL 23 QENC_INTRVL_UL 24 QENC_REAQ_MODE 25 QENC_REAQ_MODE 26 QENC_RESET_REAQ 27 ENC_DIV_FORCE_DC 28 ENC_DIV_OPEN_LOOP 29 ENC_DIV_FCLK_SEL 30 ENC_...

Page 169: ...hen QENC_NO_REAQ is set to 1 Writing a 1 to this register deletes the list of acquired lines thus next time the lines are passed over they will be acquired again Writing to this bit always resets the no re acquistiion circuit regardless of the mode as set by the QENC_REAQ_MODE However the register QENC_REAQ_MODE can be used to put the board in a mode where the no re aquisition circuit is reset aut...

Page 170: ... of the Encoder Divider is lock to the intput or is allowed to free run ENC_DIV_FCLK_ SEL R W CON16 31 29 R64 Karbon CL Karbon CXP Neon This register is reserved for future support for alternate Encoder Divider PLL Master clock frequencies Currently must be set to 0 which selects 50 MHz clock ENC_DIV_OPEN_LOOP Meaning 0 Output phased locked to input 1 Ouput runs open loop ...

Page 171: ...RATE 4 NTG_RATE 5 NTG_RATE 6 NTG_RATE 7 NTG_RATE 8 NTG_RATE 9 NTG_RATE 10 NTG_RATE 11 NTG_RATE 12 NTG_RATE 13 NTG_RATE 14 NTG_RATE 15 NTG_RATE 16 NTG_RATE 17 NTG_RATE 18 NTG_RATE 19 NTG_RATE 20 NTG_RATE 21 NTG_RATE 22 NTG_RATE 23 NTG_RATE 24 NTG_RATE 25 NTG_RATE 26 NTG_RATE 27 NTG_RATE 28 Reserved 29 Reserved 30 NTG_ONESHOT 31 NTG_TRIG_MODE ...

Page 172: ...G_ONESHOT R W CON17 30 Alta Karbon CL Karbon CXP Neon R64 This bit defines whether the NTG is free running or in one shot mode NTG_TRIG_ MODE R W CON17 31 Alta Karbon CL Karbon CXP Neon R64 This bit determines what triggers the NTG when it is in one shot mode Table 8 3 NTG clock frequency Model Frequency Karbon CL Karbon CXP Neon R64 7 3728 MHz Alta 5 000 MHz NTG_ONESHOT Mode 0 NTG is free running...

Page 173: ...e 0 ALPF 1 ALPF 2 ALPF 3 ALPF 4 ALPF 5 ALPF 6 ALPF 7 ALPF 8 ALPF 9 ALPF 10 ALPF 11 ALPF 12 ALPF 13 ALPF 14 ALPF 15 ALPF 16 ALPF 17 TOP_REV 18 TOP_REV 19 TOP_REV 20 TOP_REV 21 TOP_REV 22 TOP_REV 23 TOP_REV 24 TOP_REV 25 TOP_REV 26 TOP_REV 27 TOP_REV 28 TOP_REV 29 TOP_REV 30 NTG_INVERT 31 NTG_TIME_MODE ...

Page 174: ... lines TOP_REV RO CON9 11 0 Alta Karbon CL Karbon CXP Neon R64 Firmware revision NTG_INVERT R W CON18 30 Alta Karbon CL Karbon CXP Neon R64 This bit allows for the inversion of the New Timing Generators s NTG output See Section 3 1 for more information on the NTG NTG_TIME_ MODE R W CON18 31 Alta Karbon CL Karbon CXP Neon R64 This bit is used to scale down the frequency of the NTG clock The NTG clo...

Page 175: ... LINES_TOGO 5 LINES_TOGO 6 LINES_TOGO 7 LINES_TOGO 8 LINES_TOGO 9 LINES_TOGO 10 LINES_TOGO 11 LINES_TOGO 12 LINES_TOGO 13 LINES_TOGO 14 LINES_TOGO 15 LINES_TOGO 16 LINES_TOGO 17 ENC_DIV_N 18 ENC_DIV_N 19 ENC_DIV_N 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 176: ...n CL Karbon CXP Neon R64 This register will reflect the number of remaining lines left to be acquired till the end of the frame ENC_DIV_N R W CON19 19 17 R64 Karbon CL Karbon CXP Neon This register represents the N parameter in the encoder divider equation See Sec tion 5 1 for more information ...

Page 177: ..._EQ 5 FIFO_EQ 6 FIFO_EQ 7 FIFO_EQ 8 VID_BRL 9 VID_BRL 10 VID_BRL 11 VID_BRL 12 VID_BRL 13 VID_BRL 14 VID_BRL 15 VID_BRL 16 VIDEO_2DPM 17 VIDEO_2DPM 18 VIDEO_2DPM 19 VIDEO_2DPM 20 VIDEO_2DPM 21 VIDEO_2DPM 22 VIDEO_2DPM 23 VIDEO_2DPM 24 COLOR_MASK 25 COLOR_MASK 26 SHIFT_DSP_SELECT 27 SHIFT_DSP 28 SHIFT_DSP 29 SHIFT_DSP 30 SHIFT_DSP 31 SHIFT_DSP_LEFT ...

Page 178: ... CON20 25 24 Alta Karbon CL Karbon CXP Neon R64 This bitfield can be used to mask out color channels when acquiring color pixels for mats e g 24 bit color 36 bit color etc SHIFT_DSP_ SELECT R W CON20 26 Alta Karbon CL Karbon CXP Neon R64 This bitfield has the following properties SHIFT_DISP R W CON20 30 27 Alta Karbon CL Karbon CXP Neon R64 This register holds the shift amount for data to be displ...

Page 179: ...ON20 Register Version G 5 BitFlow Inc NEO 8 81 SHIFT_DSP_LEFT R W CON20 31 Alta Karbon CL Karbon CXP Neon R64 This bitfield has the following properties SHIFT_DSP_LEFT Meaning 0 Shift display data right 1 Shift display data left ...

Page 180: ...rd Bit Name 0 RED_GAIN 1 RED_GAIN 2 RED_GAIN 3 RED_GAIN 4 RED_GAIN 5 RED_GAIN 6 RED_GAIN 7 RED_GAIN 8 GREEN_GAIN 9 GREEN_GAIN 10 GREEN_GAIN 11 GREEN_GAIN 12 GREEN_GAIN 13 GREEN_GAIN 14 GREEN_GAIN 15 GREEN_GAIN 16 BLUE_GAIN 17 BLUE_GAIN 18 BLUE_GAIN 19 BLUE_GAIN 20 BLUE_GAIN 21 BLUE_GAIN 22 BLUE_GAIN 23 BLUE_GAIN 24 DECODER_OUT 25 DECODER_OUT 26 DECODER_OUT 27 Reserved 28 BAYER_BIT_DEPTH 29 BAYER_B...

Page 181: ...own by 64 Numbers above 255 are clipped to 255 saturation effect BLUE_GAIN R W CON21 23 16 Karbon CL Karbon CXP Neon R64 This register controls the gain of the blue channel The video value is multiplied by the value in BLUE_GAIN and after that scaled down by 64 Numbers above 255 are clipped to 255 saturation effect DECODER_OUT R W CON21 26 24 Karbon CL Karbon CXP Neon R64 These bits controls the o...

Page 182: ...0 Karbon CL Karbon CXP Neon R64 These bits control the starting phase of the Bayer decoder This register is set based on the arrangement of the color matrix in the camera s CCD BAYER_10_BIT Meaning 0 00b 8 bit pixels 1 01b 12 bit pixels 2 10b 10 bit pixels 3 11b Reserved DECODER_PHASE Meaning 0 00b First two pixels Blue Green 1 01b First two pixels Green Blue 2 10b First two pixels Red Green 3 11b...

Page 183: ..._DATA 5 FLASH_DATA 6 FLASH_DATA 7 FLASH_DATA 8 FLASH_DATA 9 FLASH_DATA 10 FLASH_DATA 11 FLASH_DATA 12 FLASH_DATA 13 FLASH_DATA 14 FLASH_DATA 15 FLASH_DATA 16 SCAN_STEP 17 SCAN_STEP 18 SCAN_STEP 19 SCAN_STEP 20 SCAN_STEP 21 SCAN_STEP 22 SCAN_STEP 23 SCAN_STEP 24 SCAN_STEP 25 SCAN_STEP 26 SCAN_STEP 27 SCAN_STEP 28 SCAN_STEP 29 SCAN_STEP 30 SCAN_STEP 31 SCAN_STEP ...

Page 184: ...or writing to the flash memory on the board SCAN_STEP R W CON22 31 16 Karbon CL Karbon CXP Neon This bitfield controls the number of encoder pulses that must occur before a trigger is issued to the system See SCAN_STEP_TRIG for more information The Scan Step cir cuit takes into account the interval and re acquisition functions ...

Page 185: ...DPM_SIZE 6 DPM_SIZE 7 DPM_SIZE 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 CTAB_INT_CON 16 LINES_PER_INT 17 LINES_PER_INT 18 LINES_PER_INT 19 LINES_PER_INT 20 LINES_PER_INT 21 LINES_PER_INT 22 LINES_PER_INT 23 LINES_PER_INT 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 186: ...t LINES_PER_INT RW CON23 23 16 Karbon CL Karbon CXP Neon Alta This bit controls the lines per interrupt circuit This circuit can be used to create a peri odic interrupt on the CTAB interrupt The interrupt rate will be every N lines where N is the value programmed in this register Note that CTAB_INT_CON must be set to one in order for the interrupts to be seen by the host CTAB_INT_CON Meaning 0 CTA...

Page 187: ...LUT_HOST_DATA 2 LUT_HOST_DATA 3 LUT_HOST_DATA 4 LUT_HOST_DATA 5 LUT_HOST_DATA 6 LUT_HOST_DATA 7 LUT_HOST_DATA 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 LUT_ON 16 LUT_HOST_ADDR 17 LUT_HOST_ADDR 18 LUT_HOST_ADDR 19 LUT_HOST_ADDR 20 LUT_HOST_ADDR 21 LUT_HOST_ADDR 22 LUT_HOST_ADDR 23 LUT_HOST_ADDR 24 LUT_BANK 25 LUT_BANK 26 Reserved 27 LUT_DATA_WRITE_ SEL 28 ...

Page 188: ...e LUT s memory location as specified by LUT_HOST_ADDR The procedure to read data from the LUT is as follows Set LUT_HOST_ACCESS to 1 Set LUT_DATA_WRITE_SEL to 0 Set LUT_BANK to the desired bank to read Set LUT_HOST_LANE to the desired LUT lane to read Set LUT_HOST_ADDR to the desired LUT location to read Read LUT_HOST_DATA the value returned in this register is the value in the LUT s memory LUT_ON...

Page 189: ...transferred to the LUT memory When LUT_DATA_WRITE_SEL is set to 0 writing to this bit has no effect See LUT_HOST_DATA for more information LUT_BANK Meaning 0 000b Host access to bank 0 data passes through bank 0 1 001b Host access to bank 1 data passes through bank 1 2 010b Host access to bank 2 data passes through bank 2 3 011b Host access to bank 3 data passes through bank 3 LUT_DATA_WRITE_SEL M...

Page 190: ...tFlow Inc Version G 5 LUT_HOST_ ACCESS R W CON24 31 Alta Karbon CL Karbon CXP Neon R64 These bits turns on and off host access to the LUT DECODER_OUT Meaning 0 The LUT cannot be accessed by the host 1 The LUT can be accessed by the host ...

Page 191: ...DELAY_TAP1_SEL 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 192: ...r DELAY_TAP1_ SEL R W CON25 3 Alta Karbon CL Karbon CXP Neon R64 This bit selects the register that controls the delay for tap 1 Tap 0 is always controlled by the register DELAY DELAY_TAP1 Meaning 0 000b HAW is not delayed 1 001b HAW is delayed by 1 clocks 2 010b HAW is delayed by 2 clocks 3 011b HAW is delayed by 3 clocks 4 100b HAW is delayed by 4 clocks 5 101b HAW is delayed by 5 clocks 6 11ob ...

Page 193: ...NTG_EXPOSURE 7 NTG_EXPOSURE 8 NTG_EXPOSURE 9 NTG_EXPOSURE 10 NTG_EXPOSURE 11 NTG_EXPOSURE 12 NTG_EXPOSURE 13 NTG_EXPOSURE 14 NTG_EXPOSURE 15 NTG_EXPOSURE 16 NTG_EXPOSURE 17 NTG_EXPOSURE 18 NTG_EXPOSURE 19 NTG_EXPOSURE 20 NTG_EXPOSURE 21 NTG_EXPOSURE 22 NTG_EXPOSURE 23 NTG_EXPOSURE 24 NTG_EXPOSURE 25 NTG_EXPOSURE 26 NTG_EXPOSURE 27 NTG_EXPOSURE 28 Reserved 29 Reserved 30 NTG_RESET 31 NTG_SLAVE ...

Page 194: ... NTG_RESET WO CON26 30 Alta Karbon CL Karbon CXP Neon R64 This bit resets the NTG s internal counter Writing a 1 to this bit resets the counter to 0 NTG_SLAVE R W CON26 31 Alta Karbon CL Karbon CXP Neon R64 This bit determines how whether the NTG is running on its own timing or slave to the master VFG Note This bit must be set to 0 for the master VFG Table 8 4 NTG clock frequency Model Frequency K...

Page 195: ...FLASH_ADDR 5 FLASH_ADDR 6 FLASH_ADDR 7 FLASH_ADDR 8 FLASH_ADDR 9 FLASH_ADDR 10 FLASH_ADDR 11 FLASH_ADDR 12 FLASH_ADDR 13 FLASH_ADDR 14 FLASH_ADDR 15 FLASH_ADDR 16 FLASH_ADDR 17 FLASH_ADDR 18 FLASH_ADDR 19 FLASH_ADDR 20 FLASH_ADDR 21 FLASH_ADDR 22 FLASH_ADDR 23 FLASH_ADDR 24 FLASH_ADDR 25 FLASH_ADDR 26 FLASH_WP 27 FLASH_RST 28 FALSH_BE 29 FLASH_CE 30 FLASH_OE 31 FLASH_WE ...

Page 196: ... CL Karbon CXP This register is used for read write to the on board flash memory FLASH_BE R W CON27 28 Karbon CL Karbon CXP This register is used for read write to the on board flash memory FLASH_CE R W CON27 29 Karbon CL Karbon CXP This register is used for read write to the on board flash memory FLASH_OE R W CON27 30 Karbon CL Karbon CXP This register is used for read write to the on board flash...

Page 197: ...K_OUT_FREQ 3 CLK_POL 4 CLK_OUT_LEVEL 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 198: ...n DIF This bit controls the clock polarity that used to sample the incoming digital data CLK_OUT_LEVEL R W CON27 4 Neon DIF This bit controls the level of the output clock CLK_OUT_FREQ Meaning 0 000b DC 1 001b 1 25 MHz 2 010b 5 0 MHz 3 011b 10 MHz 4 100b 15 MHz 5 101b 20 MHz 6 110b 30 MHz 7 111b Reserved CLK_POL Meaning 0 Samples on rising edge 1 Sample on falling edge CLK_OUT_LEVEL Meaning 0 Cloc...

Page 199: ...MEM_ADDR_LO 5 MEM_ADDR_LO 6 MEM_ADDR_LO 7 MEM_ADDR_LO 8 MEM_ADDR_LO 9 MEM_ADDR_LO 10 MEM_ADDR_LO 11 MEM_ADDR_LO 12 MEM_ADDR_LO 13 MEM_ADDR_LO 14 MEM_ADDR_LO 15 MEM_ADDR_LO 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 200: ...r The Neon NEO 8 102 BitFlow Inc Version G 5 MEM_ADDR_LO R W CON25 15 0 Neon This register is the lower 16 bits used to access the flash or ROM memory on boards that have it This is not a user programmable register ...

Page 201: ...3 MEM_ADDR_HI 4 MEM_CS 5 MEM_WRITE 6 DWNLD_MODE 7 DWNLD_MODE 8 MEM_DATA 9 MEM_DATA 10 MEM_DATA 11 MEM_DATA 12 MEM_DATA 13 MEM_DATA 14 MEM_DATA 15 MEM_DATA 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 202: ...s both host access and FPGA download source This is not a user programmable register MEM_WRITE R W CON37 5 Alta Neon Used to write to SRAM Writing a 1 to this bit force the data in MEM_DATA to be writ ten to the address in MEM_ADDR DWNLD_MODE R W CON37 7 6 Alta Neon Future use MEM_DATA R W CON37 15 8 Neon This bitfield provides data access used when reading or writing the flash or ROM on boards th...

Page 203: ...Reserved 4 POCL_SENSE 5 POCL_CLK_ DETECTED 6 POCL_DETECTED 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 204: ...medi ately remove the power if it sense that the pixel clock has stopped POCL_SENSE RO CON38 3 Neon This register indicates that the PoCL state machine is the sense state In this state the powers has not been applied and the PoCL state machine is watching the imped ance on the CL cable If the impedance of a PoCL camera is detected the power will be applied It a short is detected indicating a legac...

Page 205: ...state This state is the normal powered up steady state for the PoCL state machine POCL_ DETECTED RO CON38 6 Neon This register indicates that the PoCL state machine has detected a PoCL camera POCL_SENSE Meaning 0 The PoCL state machine is not in the sense state 1 The PoCL state machine is in the sense state POCL_CLK_DETECTED Meaning 0 The PoCL state machine has not detected a camera pixel clock 1 ...

Page 206: ..._PORT_ADDR 5 AFE_PORT_ADDR 6 AFE_PORT_ADDR 7 AFE_PORT_ADDR 8 AFE_PORT_WRITE 9 AFE_PORT_ACCESS 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 207: ...sed as the address for subsequent read write operations AFE_PORT_ WRITE R W CON40 8 Alta Determines the AFE access operation AFE_PORT_ ACCESS WO CON40 9 Alta Writing a 1 to the bit causes the AFE to be accessed The type of operation depends on the AFE_PORT_WRITE bit AFE_PORT_WRITE Meaning 0 The next access operation will be a read 1 The next access operation will be a write ...

Page 208: ...ORT_DATA 5 AFE_PORT_DATA 6 AFE_PORT_DATA 7 AFE_PORT_DATA 8 AFE_PORT_BUSY 9 AFE_PORT_ERROR 10 AFE_PORT_RESET 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 209: ...ailable in this bitfield after the read operation is complete AFE_PORT_ BUSY RO CON41 8 Alta Used when accessing the AFE AFE_PORT_ ERROR RO CON41 9 Alta A 1 in this bit indicates that an error occurred during the last AFE access operation AFE_PORT_ RESET WO CON41 10 Alta Writing a 1 to the bit resets the AFE access mechanism AFE_PORT_BUSY Meaning 0 The AFE access operation is completed 1 The AFE a...

Page 210: ... 2 RD_WEN 3 Reserved 4 RD_HD 5 RD_VD 6 SWAP_LINES 7 FI_POL 8 SOE 9 SOE 10 ACQ_IV 11 FEN_SEL 12 FEN_SEL 13 FEN_SEL 14 HD_SEL 15 HD_SEL 16 HD_SEL 17 VD_SEL 18 VD_SEL 19 VD_SEL 20 GEN_IV 21 Reserved 22 MID 23 MID 24 ENDIAN 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 211: ... CON42 2 Alta This bit indicates the current status of the of the WEN I O signal RD_HD R W CON42 4 Alta This bit indicates the current status of the of the horizontal sync HD I O signal FI Meaning 0 The field index is low 1 The field index is high FI Meaning 0 The field index was low at the start of acquisition 1 The field index was high at the start of acquisition RD_HD Meaning 0 The WEN input is...

Page 212: ...CON42 7 Alta Used to swap the polarity of the field index signal needed for some interlaced cam eras SOE R W CON42 9 8 Alta This bits dictates which field from an interlaced camera initiates acquisition RD_VD Meaning 0 The VD input is currently low 1 The VD input is currently high SWAP_LINES Meaning 0 Do not swap fields 1 Swap fields FI_POL Meaning 0 Normal polarity 1 Invert polarity SOE Meaning 0...

Page 213: ... R W CON42 16 14 Alta This bitfield controls the sorce of the HD output signal ACQIV Meaning 0 Incoming video is non interlaced 1 Incoming video is interlaced FEN_SEL Meaning 0 000b Use VD signal from AFE 1 001b Use WEN input signal 2 010b Reserved 3 011b Reserved 4 100b Reserved 5 101b Reserved 6 110b Reserved 7 111b Reserved HD_SEL Meaning 0 000b 1 001b HD is an output source is this VFG s Video...

Page 214: ...n be read from all the other VFGs This register does not control anything 4 100b HD is an output source is the AFE s detected HD sig nal 5 101b Reserved 6 110b Reserved 7 111b Reserved HD_SEL Meaning VD_SEL Meaning 0 000b 1 001b VD is an output source is this VFG s Video Generator 2 010b VD is an output source is the master VFG s Video Generator 3 011b VD is an output source the the CC4 signal 4 1...

Page 215: ... Registers CON42 Register Version G 5 BitFlow Inc NEO 8 117 ENDIAN R W CON42 24 Alta This bit is used to select the endianness of the video output ENDIAN Meaning 0 Little endian Intel mode 1 Big endian motorola mode ...

Page 216: ..._PERIOD 6 GEN_H_PERIOD 7 GEN_H_PERIOD 8 GEN_H_PERIOD 9 GEN_H_PERIOD 10 GEN_H_PERIOD 11 GEN_H_PERIOD 12 GEN_H_PERIOD 13 GEN_H_PERIOD 14 GEN_H_PERIOD 15 GEN_H_PERIOD 16 GEN_H_LOW 17 GEN_H_LOW 18 GEN_H_LOW 19 GEN_H_LOW 20 GEN_H_LOW 21 GEN_H_LOW 22 GEN_H_LOW 23 GEN_H_LOW 24 GEN_H_LOW 25 GEN_H_LOW 26 GEN_H_LOW 27 GEN_H_LOW 28 GEN_H_LOW 29 GEN_H_LOW 30 GEN_H_LOW 31 GEN_H_LOW ...

Page 217: ... Control Registers CON43 Register Version G 5 BitFlow Inc NEO 8 119 GEN_H_PERIOD R W CON43 15 0 Alta Horizontal period of Video Generator GEN_H_LOW R W CON43 15 0 Alta Horizontal low period of Video Generator ...

Page 218: ..._PERIOD 6 GEN_V_PERIOD 7 GEN_V_PERIOD 8 GEN_V_PERIOD 9 GEN_V_PERIOD 10 GEN_V_PERIOD 11 GEN_V_PERIOD 12 GEN_V_PERIOD 13 GEN_V_PERIOD 14 GEN_V_PERIOD 15 GEN_V_PERIOD 16 GEN_V_LOW 17 GEN_V_LOW 18 GEN_V_LOW 19 GEN_V_LOW 20 GEN_V_LOW 21 GEN_V_LOW 22 GEN_V_LOW 23 GEN_V_LOW 24 GEN_V_LOW 25 GEN_V_LOW 26 GEN_V_LOW 27 GEN_V_LOW 28 GEN_V_LOW 29 GEN_V_LOW 30 GEN_V_LOW 31 GEN_V_LOW ...

Page 219: ...ra Control Registers CON44 Register Version G 5 BitFlow Inc NEO 8 121 GEN_V_PERIOD R W CON43 15 0 Alta Vertical period of Video Generator GEN_V_LOW R W CON43 15 0 Alta Vertical low period of Video Generator ...

Page 220: ...NT 6 QENC_COUNT 7 QENC_COUNT 8 QENC_COUNT 9 QENC_COUNT 10 QENC_COUNT 11 QENC_COUNT 12 QENC_COUNT 13 QENC_COUNT 14 QENC_COUNT 15 QENC_COUNT 16 QENC_COUNT 17 QENC_COUNT 18 QENC_COUNT 19 QENC_COUNT 20 QENC_COUNT 21 QENC_COUNT 22 QENC_COUNT 23 QENC_COUNT 24 QENC_PHASEA 25 QENC_PHASEB 26 QENC_DIR 27 QENC_INTRVL_IN 28 QENC_NEW_LINES 29 Reserved 30 Reserved 31 Reserved ...

Page 221: ...oder phase QENC_DIR RO CON51 26 Karbon CL Karbon CXP Neon This bit displays the current quadrature encoder direction QENC_INTRVL_ IN RO CON51 27 Karbon CL Karbon CXP Neon This bit indicates the current status of the quadrature encoder if the system is in inter val mode see QENC_INTRVL_MODE QENC_DIR Meaning 0 Direction is negative 1 Direction is positive QENC_INTRVL_IN Meaning 0 System is not insid...

Page 222: ...e When QENC_NO_REAQ 1 only lines that have not yet been scanned are acquired This bit can be used to determine of new lines are being traversed or if the system has backed up and is revisiting old lines QENC_NEW_LINES Meaning 0 The system is traversing lines that have already been visited If QENC_NO_REAQ 1 lines are not being acquired 1 The system is traversing new lines Lines are being acquired ...

Page 223: ...oduction This section enumerates all of the registers that control DMA on boards using the PLDA DMA engine This includes the Alta the Karbon and the Neon families This chapter also covers the scatter gather DMA instructions Quads or QTabs The for matting of the register sections is explained in Section 8 2 ...

Page 224: ...QUAD_PTR_LO 10 FIRST_QUAD_PTR_LO 11 FIRST_QUAD_PTR_LO 12 FIRST_QUAD_PTR_LO 13 FIRST_QUAD_PTR_LO 14 FIRST_QUAD_PTR_LO 15 FIRST_QUAD_PTR_LO 16 FIRST_QUAD_PTR_LO 17 FIRST_QUAD_PTR_LO 18 FIRST_QUAD_PTR_LO 19 FIRST_QUAD_PTR_LO 20 FIRST_QUAD_PTR_LO 21 FIRST_QUAD_PTR_LO 22 FIRST_QUAD_PTR_LO 23 FIRST_QUAD_PTR_LO 24 FIRST_QUAD_PTR_LO 25 FIRST_QUAD_PTR_LO 26 FIRST_QUAD_PTR_LO 27 FIRST_QUAD_PTR_LO 28 FIRST_Q...

Page 225: ...Alta Karbon CL Karbon CXP Neon This is the low word of the 64 bit address of the first DMA scatter gather instruction in a chain of instructions This register can be written at any time but the DMA engine only loads this value when byte count as set by CHAIN_DATA_SIZE_LO CHAIN_ DATA_SIZE_HI goes to zero ...

Page 226: ...QUAD_PTR_HI 10 FIRST_QUAD_PTR_HI 11 FIRST_QUAD_PTR_HI 12 FIRST_QUAD_PTR_HI 13 FIRST_QUAD_PTR_HI 14 FIRST_QUAD_PTR_HI 15 FIRST_QUAD_PTR_HI 16 FIRST_QUAD_PTR_HI 17 FIRST_QUAD_PTR_HI 18 FIRST_QUAD_PTR_HI 19 FIRST_QUAD_PTR_HI 20 FIRST_QUAD_PTR_HI 21 FIRST_QUAD_PTR_HI 22 FIRST_QUAD_PTR_HI 23 FIRST_QUAD_PTR_HI 24 FIRST_QUAD_PTR_HI 25 FIRST_QUAD_PTR_HI 26 FIRST_QUAD_PTR_HI 27 FIRST_QUAD_PTR_HI 28 FIRST_Q...

Page 227: ...lta Karbon CL Karbon CXP Neon This is the high word of the 64 bit address of the first DMA scatter gather instruction in a chain of instructions This register can be written at any time but the DMA engine only loads this value when byte count as set by CHAIN_DATA_SIZE_LO CHAIN_ DATA_SIZE_HI goes to zero ...

Page 228: ...ZE_LO 10 CHAIN_DATA_SIZE_LO 11 CHAIN_DATA_SIZE_LO 12 CHAIN_DATA_SIZE_LO 13 CHAIN_DATA_SIZE_LO 14 CHAIN_DATA_SIZE_LO 15 CHAIN_DATA_SIZE_LO 16 CHAIN_DATA_SIZE_LO 17 CHAIN_DATA_SIZE_LO 18 CHAIN_DATA_SIZE_LO 19 CHAIN_DATA_SIZE_LO 20 CHAIN_DATA_SIZE_LO 21 CHAIN_DATA_SIZE_LO 22 CHAIN_DATA_SIZE_LO 23 CHAIN_DATA_SIZE_LO 24 CHAIN_DATA_SIZE_LO 25 CHAIN_DATA_SIZE_LO 26 CHAIN_DATA_SIZE_LO 27 CHAIN_DATA_SIZE_L...

Page 229: ...ord of the 64 bit number of bytes in the chain The value in this register is loaded into the DMA engine when DMA is initiated This value is then decremented every DMA transfer When the count reached zero this value in this register is reloaded into the DMA engine and the first scatter gather instruction pointed to by FIRST_QUAD_PTR_HI and FIRST_QUAD_PTR_LO is loaded ...

Page 230: ...ZE_HI 10 CHAIN_DATA_SIZE_HI 11 CHAIN_DATA_SIZE_HI 12 CHAIN_DATA_SIZE_HI 13 CHAIN_DATA_SIZE_HI 14 CHAIN_DATA_SIZE_HI 15 CHAIN_DATA_SIZE_HI 16 CHAIN_DATA_SIZE_HI 17 CHAIN_DATA_SIZE_HI 18 CHAIN_DATA_SIZE_HI 19 CHAIN_DATA_SIZE_HI 20 CHAIN_DATA_SIZE_HI 21 CHAIN_DATA_SIZE_HI 22 CHAIN_DATA_SIZE_HI 23 CHAIN_DATA_SIZE_HI 24 CHAIN_DATA_SIZE_HI 25 CHAIN_DATA_SIZE_HI 26 CHAIN_DATA_SIZE_HI 27 CHAIN_DATA_SIZE_H...

Page 231: ... the 64 bit number bytes in the chain The value in this register is loaded into the DMA engine when DMA is initiated This value is then decremented every DMA transfer When the count reached zero this value in this register is reloaded into the DMA engine and the first scatter gather instruction pointed to by FIRST_QUAD_PTR_HI and FIRST_QUAD_PTR_LO is loaded ...

Page 232: ...OGO_LO 10 CHAIN_DATA_TOGO_LO 11 CHAIN_DATA_TOGO_LO 12 CHAIN_DATA_TOGO_LO 13 CHAIN_DATA_TOGO_LO 14 CHAIN_DATA_TOGO_LO 15 CHAIN_DATA_TOGO_LO 16 CHAIN_DATA_TOGO_LO 17 CHAIN_DATA_TOGO_LO 18 CHAIN_DATA_TOGO_LO 19 CHAIN_DATA_TOGO_LO 20 CHAIN_DATA_TOGO_LO 21 CHAIN_DATA_TOGO_LO 22 CHAIN_DATA_TOGO_LO 23 CHAIN_DATA_TOGO_LO 24 CHAIN_DATA_TOGO_LO 25 CHAIN_DATA_TOGO_LO 26 CHAIN_DATA_TOGO_LO 27 CHAIN_DATA_TOGO_...

Page 233: ... Alta DMA CON32 Register Version G 5 BitFlow Inc NEO 9 11 CHAIN_DATA_ TOGO_LO RO CON32 31 0 Alta Karbon CL Karbon CXP Neon This register indicates the low word of the 64 bit number of bytes remaining the DMA chain ...

Page 234: ...OGO_HI 10 CHAIN_DATA_TOGO_HI 11 CHAIN_DATA_TOGO_HI 12 CHAIN_DATA_TOGO_HI 13 CHAIN_DATA_TOGO_HI 14 CHAIN_DATA_TOGO_HI 15 CHAIN_DATA_TOGO_HI 16 CHAIN_DATA_TOGO_HI 17 CHAIN_DATA_TOGO_HI 18 CHAIN_DATA_TOGO_HI 19 CHAIN_DATA_TOGO_HI 20 CHAIN_DATA_TOGO_HI 21 CHAIN_DATA_TOGO_HI 22 CHAIN_DATA_TOGO_HI 23 CHAIN_DATA_TOGO_HI 24 CHAIN_DATA_TOGO_HI 25 CHAIN_DATA_TOGO_HI 26 CHAIN_DATA_TOGO_HI 27 CHAIN_DATA_TOGO_...

Page 235: ...Alta DMA CON33 Register Version G 5 BitFlow Inc NEO 9 13 CHAIN_DATA_ TOGO_HI RO CON33 31 0 Alta Karbon CL Karbon CXP Neon This register indicates the high word of the 64 bit number of bytes remaining the DMA chain ...

Page 236: ...DMA_STATUS 6 DMA_STATUS 7 DMA_STATUS 8 DMA_NO_RULE 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 DMA_INIT_FUNC 17 DMA_PRIORITY 18 DMA_64_BIT 19 DMA_CHAINING 20 DMA_COMMAND 21 DMA_COMMAND 22 DMA_COMMAND 23 DMA_COMMAND 24 DMA_BEN 25 DMA_BEN 26 DMA_BEN 27 DMA_BEN 28 LATCH_CONTROL 29 LATCH_CONTROL 30 Reserved 31 Reserved ...

Page 237: ... CL Karbon CXP Neon Future use DMA_STATUS RO CON34 7 4 Alta Karbon CL Karbon CXP Neon Future use DMA_NO_RULE R W CON34 8 Alta Karbon CL Karbon CXP Neon Setting this bit to a 1 will cause the DMA engine to DMA data as fast as it can It will not wait for data to be available from the acquisition engine The actual data that is DMAed will be unpredictable This bit therefore is only useful for diagnost...

Page 238: ...es whether the DMA engine will execute chaining DMA or not DMA_ COMMAND R W CON34 23 20 Alta Karbon CL Karbon CXP Neon Controls the DMA engine DMA_BEN R W CON34 27 24 Alta Karbon CL Karbon CXP Neon Future use LATCH_ CONTROL R W CON34 29 28 Alta Karbon CL Karbon CXP Neon Future use DMA_64_BIT Meaning 0 32 bit DMA operations 1 64 bit DMA operations DMA_CHAINING Meaning 0 Execute a single DMA operati...

Page 239: ... XFR_PER_INT 7 XFR_PER_INT 8 XFR_PER_INT 9 XFR_PER_INT 10 XFR_PER_INT 11 XFR_PER_INT 12 XFR_PER_INT 13 XFR_PER_INT 14 XFR_PER_INT 15 XFR_PER_INT 16 XFR_PER_INT 17 XFR_PER_INT 18 XFR_PER_INT 19 XFR_PER_INT 20 XFR_PER_INT 21 XFR_PER_INT 22 XFR_PER_INT 23 XFR_PER_INT 24 XFR_PER_INT 25 XFR_PER_INT 26 XFR_PER_INT 27 XFR_PER_INT 28 XFR_PER_INT 29 XFR_PER_INT 30 XFR_PER_INT 31 XFR_PER_INT ...

Page 240: ... 18 BitFlow Inc Version G 5 XFR_PER_INT R W CON35 31 0 Alta Karbon CL Karbon CXP Neon This register controls how often the board issues an EOF interrupt Every time XFR_ PER_INT bytes have been DMAed the board will emit an interrupt ...

Page 241: ...ather DMA instructions These are called quads because they generally consist of four words although the DMA engine only uses three words A list of instructions are called a Quad Table or QTAB Each quad con sists of the following entries 1 Destination address 2 Size of transfer 3 Next quad address The following sections document the structure of these quads ...

Page 242: ...on Address 13 Destination Address 45 Destination Address 14 Destination Address 46 Destination Address 15 Destination Address 47 Destination Address 16 Destination Address 48 Destination Address 17 Destination Address 49 Destination Address 18 Destination Address 50 Destination Address 19 Destination Address 51 Destination Address 20 Destination Address 52 Destination Address 21 Destination Addres...

Page 243: ...ata Size 5 Data Size 6 Data Size 7 Data Size 8 Data Size 9 Data Size 10 Data Size 11 Data Size 12 Data Size 13 Data Size 14 Data Size 15 Data Size 16 Data Size 17 Data Size 18 Data Size 19 Data Size 20 Data Size 21 Data Size 22 Data Size 23 Data Size 24 Data Size 25 Data Size 26 Data Size 27 Data Size 28 Data Size 29 Data Size 30 Data Size 31 Data Size ...

Page 244: ...44 Next Quad Address 13 Next Quad Address 45 Next Quad Address 14 Next Quad Address 46 Next Quad Address 15 Next Quad Address 47 Next Quad Address 16 Next Quad Address 48 Next Quad Address 17 Next Quad Address 49 Next Quad Address 18 Next Quad Address 50 Next Quad Address 19 Next Quad Address 51 Next Quad Address 20 Next Quad Address 52 Next Quad Address 21 Next Quad Address 53 Next Quad Address 2...

Page 245: ...Version G 5 BitFlow Inc NEO 10 1 Register and Memory Mapping Chapter 10 10 1 Introduction This section explains how the registers and the various chunks of memory are mapped and accessed on the Alta Karbon Neon and their virtual frame grabbers ...

Page 246: ...eon 10 2 3 DPM The DPM is 64 bit wide The DPM can be accessed as 64 bit on 64 bit boundary or as 32 bit wide on 32 bit boundary memory During acquisition GRAB SNAP the slave read from DPM is inhibited In this case data read will be always zero Note The DPM is only accessible form host on the R64 10 2 4 CTABs The CTabs for the Karbon CL and Karbon CXP Alta and Neon are implemented slightly differen...

Page 247: ...ster CON13 00 10 00 20 Camera Control Register CON14 00 10 00 28 Camera Control Register CON15 00 00 00 08 Camera Control Register CON16 00 00 00 10 Camera Control Register CON17 00 00 00 18 Camera Control Register CON18 00 00 00 20 Camera Control Register CON19 00 00 00 28 Camera Control Register CON20 00 10 00 30 Camera Control Register CON21 00 10 00 38 Camera Control Register CON22 00 00 00 30...

Page 248: ...ta Only CON50 00 00 00 E8 Alta Only CON51 00 00 00 F0 Camera Control Register CON60 00 a0 00 00 Karbon CXP Only CON61 00 a0 00 08 Karbon CXP Only CON62 00 a0 00 10 Karbon CXP Only CON63 00 a0 00 18 Karbon CXP Only CON64 00 a0 00 20 Karbon CXP Only CON65 00 a0 00 28 Karbon CXP Only CON66 00 a0 00 30 Karbon CXP Only CON67 00 a0 00 38 Karbon CXP Only CTABS 00 20 00 00 Only first 256 address populated...

Page 249: ...ten to the chip On the Alta and Neon families download is facilitated by writing to board resident SRAM This SRAM is always available on the board and is accessed indirectly Once the SRAM is loaded with new firmware the board s FPGAs can be flashed directly from the SRAM On the Karbon CXP firmware is not normally downloaded except when there is an update from the factory The mechanism for download...

Page 250: ...Flow Inc Version G 5 10 5 PCI Configuration Space and Model Revision Information Each family of boards has its own device ID as follows Alta 0x5000 Karbon 0x3000 Neon 0x4000 Information about different models and board capabilities is stored in the INFO_HI and INFO_LO registers ...

Page 251: ...erfacing Chapter 11 11 1 Introduction This chapter describes the electrical interface of the Karbon Neon R64 This includes detailed information on the all if the input and output signals In addition information is provided on recommend circuits to use when connecting to these signals ...

Page 252: ..._ FEN The unselected triggers will have no effect on the board However they can be used as general purpose inputs 11 2 2 The Optocoupled Trigger The opto coupled trigger allows the acquisition circuitry to accept a trigger signal without having a galvanic connection to the trigger source This is mandatory in some medical and industrial application The trigger information is passed as a light pulse...

Page 253: ... Interfacing Trigger Version G 5 BitFlow Inc NEO 11 3 Figure 11 1 Driver Circuit for Opto Coupled Trigger 220 SFH6325 TRIGGER_OPTO_A TRIGGER_OPTO Frame Grabber User Circuit TRIGGER_OPTO_K 7407 Opto Coupler 5V 5V ...

Page 254: ... no effect on the board However they can be used as general purpose inputs 11 3 2 The Optocoupled Encoder The opto coupled encoder allows the acquisition circuitry to accept an encoder sig nal without having a galvanic connection to the encoder source This is mandatory in some medical and industrial application The encoder information is passed as a light pulse from an on board LED that is coupled...

Page 255: ... Interfacing Encoder Version G 5 BitFlow Inc NEO 11 5 Figure 11 2 Driver Circuit for Opto Coupled Encoder 220 SFH6325 ENCODER_OPTO_A ENCODER_OPTO Frame Grabber User Circuit ENCODER_OPTO_K 7407 Opto Coupler 5V 5V ...

Page 256: ...nal signal connected to a GPIN pin is electrically high then an associated regis ter will read back one if the same signal is low then the bit will read back zero There are two different type of GPIN input pins TTL and differential LVDS For each GPIN pin there is an associated GPIN register See the pin out in the mechanical chapter to determine the actual pins each signal resides on Each frame gra...

Page 257: ...ential LVDS and Open Collector Each type is described in more detail below See the IO connector pin out tables to determine which signals are on which pins Not every frame grabber family has the same number and type of GPOUTs please see Chapter 13 for details 11 5 2 GPOUT Open Collector Drivers The GPOUT open collector driver circuit can be used in two different ways The circuit can be used to dri...

Page 258: ...n collector GPOUT in the factory configuration can drive an opto coupling device The user must supply the 5V to this LED and the two systems must have their grounds connected In this configuration the board and the user s system must have a common electrical ground GPOUT JP3 JP2 12V 5V 5V GPOUT_VCC GPOUT5_OC GND 7407 1K 220 680 User Circuit Opto Coupler 1 2 3 Frame Grabber ...

Page 259: ...wer to the user s LED is supplied by the board s 5V through a 220 Ohm resistor This is achieved by inserting the short in position 1 2 at JP1 The jumper at JP2 is removed The open collector driver will sink the current from the LED There is no gal vanic connection between the board and the user s circuit Information is passed from the board to the user as light transmitted by the LED and received ...

Page 260: ...CC is controlled by the corresponding CCx_CON bitfield Table 11 1 illus trates the source for each CCx as a function of its associated CCx_CON bitfield Table 11 1 CCx_CON CCx_CON CCx Source 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running on board signal generator Controlled by FREE_RUN_RATE and FREE_ RUN_HIGH 4 100b Internally generated clock Frequency set by CFR...

Page 261: ...mum Input Pixel Clock Frequency DIF 85 MHz Minimum Input Pixel Clock Frequency DIF 0 MHz Maximum Pixels Per Line 1 tap 262 144 256K Pixels Section 12 2 Maximum Lines Per Frame 131 072 128K Lines Section 12 3 Minimum clocks between lines 16 Clocks Minimum lines between frames 0 Lines Minimum pixel clocks between frames 16 Clocks Minimum trigger pulse 600 Nanoseconds Minimum encoder pulse 600 Nanose...

Page 262: ... Version G 5 Mechanical dimensions 6 8 x 4 2 Inches Mechanical dimensions 17 4 x 10 67 Centimeters Minimum UART baud rate 110 Bits Second Maximum UART baud rate 230K Bits Second Table 12 1 Neon Specifications Specifications Value Units Details ...

Page 263: ...ollowing formula Max_pix_per_line 256K x Taps Taps is the number of taps A tap supplies a whole pixel Examples A two tap camera that supplies odd even pixels Max_pix_per_line 512K An RGB camera that supplies RGB over 24 bits Max_pix_per_line 256K as every clock the camera supplies one single pixel A four tap two segments each left right Max_pix_per_line 1M ...

Page 264: ... lines per frame is given by the follow ing formula Max_lines_per_frame 128K x Line_taps Line_taps is the number of taps that supply a whole line Examples A one tap camera Max_lines_per_frame 128K A two tap camera that supplies odd even lines Max_lines_per_frame 256K A two tap camera that supplies odd even pixels Max_lines_per_frame 128K ...

Page 265: ...power an attached PoCL camera or cameras The PoCL specification allows for up to 0 5 Amps at 12V of current to be drawn Thus the maximum power the NEO PCE CLB could draw with a PoCL camera attached is 0 575 Amps on the 12 V rail and the maximum for the NEO PCE CLD NEO PCE CLM is 1 075 Amps on the 12 V rail Finally the NEO PCE CLQ can draw up to 2 075 Amps on the 12 V rail ...

Page 266: ...Power Consumption The Neon NEO 12 6 BitFlow Inc Version G 5 ...

Page 267: ...eader connector Table 13 1 shows the number and type of connectors The Neon Dif supports one differential camera up to 32 bits in width This requires two connectors the main D Sub connector which supports 16 bits plus camera con trol signals and serial communications the second connector on the top edge of the board which requires a ribbon cable mass terminated type of connector which sup ports an...

Page 268: ... NEO PCE CLB revision 1 is shown in Figure 13 1 Figure 13 1 NEO PCE CLB Revision 1 Layout The revision 1 NEO PCE CLB is available with two different I O configuration See Section 13 11 and Section 13 12 for detailed information on the different pin outs of the connector P10 CL1 P10 S1 1 S1 2 Jumper Set 1 PCI Express x4 Connector ...

Page 269: ...e 13 2 Figure 13 2 NEO PCE CLB Revision 2 Layout The revision 2 version of the NEO PCE CLB board only comes in one configuration However all of the alternate signals that were available with the alternate version of the revision 1 NEO PCE CLB are still available via the use of the switches S2 to S7 CL1 P10 S2 S3 S4 S7 S6 S5 Jumper Set 1 PCI Express x4 Connector S1 1 S1 2 ...

Page 270: ...NEO 13 4 BitFlow Inc Version G 5 13 4 The NEO PCE CLD The mechanical layout of the NEO PCE CLD are shown in Figure 13 3 Figure 13 3 The NEO PCE CLD Layout CL1 CL2 P1 Denotes Pin 1 PCI Express x4 Connector Jumper Set 1 S1 1 S1 2 ...

Page 271: ... CL connector is mounted on a separate bracket There is a short flex cable that connects the this bracket to the NEO PCE CLQ main board The flex cable allows the fourth connector to be located on either side of the main board and can be up to three slots away from the main board The fourth con nectors is shown in Figure 13 5 CL1 CL2 CL3 Denotes Pin 1 PCI Express x4 Connector S1 1 S1 2 Flex Cable C...

Page 272: ...The NEO PCE CLQ The Neon NEO 13 6 BitFlow Inc Version G 5 Figure 13 5 NEO PCE CLQ CL4 Connector CL4 Flex Cable Connector ...

Page 273: ...hanical The NEO PCE DIF Version G 5 BitFlow Inc NEO 13 7 13 6 The NEO PCE DIF The mechanical layout of the NEO PCE DIF Figure 13 6 Figure 13 6 NEO PCE DIF Layout P7 P2 P3 PCI Express x4 Connector S1 1 S1 2 ...

Page 274: ...2 Auxiliary Connector Digital Data upper 16 bits P3 I O connector P7 Main Connector Digital Data lower 16 bits and I O 13 7 1 The CL Connectors The CL connectors are for connecting Camera Link cameras Table 13 2 illustrates how to connect the Neon to a Camera Link Camera 13 7 2 The I O Connectors The I O connector P10 on NEO PCE CLB and P1 on the NEO PCE CLD NEO PCE CLQ and P2 on the NEO PCE CDIF ...

Page 275: ...ow Inc NEO 13 9 devices Some of the inputs have specific functions for example the Trigger and Encoder and some are general purpose for example GPIN0 whose state can be read by software These signals are described in detail in the following sections ...

Page 276: ...tead there are two GPOUT5 signals VFG0_GPOUT5 and VFG1_GPOUT5 That is each VFG has one GPOUT5 signal and no GPOUT6 signal When using the table below substitue VFG0_ GOUT5 for GPOUT5 and VFG1_GOUT5 for GPOUT6 Table 13 3 Jumper Set 1 Jumper Position 1 2 Position 2 3 No Jumper JP1 5 Volt connected to GPOUT5_VCC through a 220 Ohm resistor 12 Volt connected to GPOUT5_VCC through a 680 Ohm resistor Powe...

Page 277: ...ield 13 9 2 Switch S2 NEO PCE CLB Revision 2 Only The switch S2 is used to control the type of signals that are present on the Pins 7 and 14 o f P10 connector These settings are illustrates in Table 13 5 13 9 3 Switches S3 and S6 NEO PCE CLB Revision 2 Only The switches S3 and S6 are used to control the type of signals that are present on the Pins 2 and 10 o f P10 connector These settings are illu...

Page 278: ...3 7 13 9 5 Switch S5 NEO PCE CLB Revision 2 Only The switch S5 is used to control the type of signals that are present on the Pins 3 and 11 o f P10 connector These settings are illustrates in Table 13 8 Table 13 7 S4 and S7 Switch Setting S4 S7 Pin1 Pin 9 down down TRIGGER TRIGGER down up TRIGGER_TTL GND up down TRIGGER_OPTO_A TRIGGER_OPTO_K up up TRIGGER_OPTO_A TRIGGER_OPTO_K Table 13 8 S5 Switch...

Page 279: ...ification for frame grabbers This specification is maintained by the Automated Imaging Associa tion Please contact this organization for a copy of the specification At the time of this printing it is available on the web at www machinevisiononline org It is important to understand that some of these signals are the output of a high speed serial converter chip and require special instrumentation to...

Page 280: ...he connector P10 is only on the NEO PCE CLB Revision 1 model Neon Table 13 9 P10 I O Connector Standard Configuration Pin I O Signal Comment 1 In TRIGGER LVDS 2 In ENCODER LVDS 3 Out GPOUT5_VCC Pull up or power for the open collector driver 4 Out GPOUT3 TTL 5 GND Ground 6 In GPIN1 TTL 7 Out GPOUT0 LVDS 8 In GPIN2 LVDS 9 In TRIGGER LVDS 10 In ENCODER LVDS 11 Out GPOUT5_OC Open collector driver 12 O...

Page 281: ...le as a special ordering option from BitFlow Table 13 10 P10 I O Connector Alternate Configuration Pin I O Signal Comment 1 Out GPOUT1 LVDS 2 Out GPOUT2 LVDS 3 In GPIN3 LVDS 4 In TRIGGER_OPTO_A Anode of optocoupling sensor 5 GND Ground 6 In ENCODER_OPTO_A Anode of optocoupling sensor 7 Out GPOUT6_VCC Pull up or power for the open collector driver 8 In TRIGGER_TTL TTL 9 Out GPOUT1 LVDS 10 Out GPOUT...

Page 282: ... can also be used as ENCODERB_TTL Note The input GPIN2 can also be used as ENCODERB Table 13 11 P10 I O Connector NEO PCE CLB Revision 2 Pin I O Default Signal Alternate 1 Alternate 2 Comment 1 In TRIGGER TRIGGER_TTL TRIGGER_OPTO_A See switches S4 and S7 2 In ENCODER ENCODER_TTL ENCODER_OPTO_A See switches S3 and S6 3 Out GPOUT5_VCC GPOUT2 See switch S5 4 Out GPOUT3_TTL 5 GND 6 In GPIN1_TTL 7 Out ...

Page 283: ...ERB LVDS also VFG1_GPIN0 8 In VFG1_ENCODERB LVDS also VFG1_GPIN0 9 In VFG1_ENCODERA LVDS 10 In VFG1_ENCODERA LVDS 11 In VFG1_TRIGGER LVDS 12 In VFG1_TRIGGER LVDS 13 Out VFG0_GPOUT0 LVDS 14 Out VFG0_GPOUT0 LVDS 15 Out VFG0_GPOUT1 LVDS 16 Out VFG0_GPOUT1 LVDS 17 Out VFG1_GPOUT0 LVDS 18 Out VFG1_GPOUT0 LVDS 19 Out VFG1_GPOUT1 LVDS 20 Out VFG1_GPOUT1 LVDS 21 In VFG0_TRIGGER_OPTO_A Anode of optocouplin...

Page 284: ... driver 29 GND 30 GND 31 In VFG0_TRIGGER_TTL TTL 32 In VFG0_ENCODERA_TTL TTL 33 In VFG0_ENCODERB_TTL TTL also VFG0_GPIN1_TTL 34 In VFG1_ENCODERB_TTL TTL also VFG1_GPIN1_TTL 35 In VFG1_TRIGGER_TTL TTL 36 In VFG1_ENCODERA_TTL TTL 37 Out VFG0_GPOUT2_TTL TTL 38 Out VFG0_GPOUT3_TTL TTL 39 Out VFG1_GPOUT2_TTL TTL 40 Out VFG1_GPOUT3_TTL TTL Table 13 12 P1 I O Connector Pin I O Signal Comment ...

Page 285: ...TL TTL 4 In VFG0_ENCODERA_TTL TTL 5 Out VFG0_GPOUT0_TTL TTL 6 Out VFG0_GPOUT1_TTL TTL 7 In VFG1_TRIGGER LVDS 8 In VFG1_TRIGGER LVDS 9 In VFG1_TRIGGER_TTL TTL 10 In VFG1_ENCODERA_TTL TTL 11 Out VFG1_GPOUT0_TTL TTL 12 Out VFG1_GPOUT1_TTL TTL 13 In VFG2_TRIGGER LVDS 14 In VFG2_TRIGGER LVDS 15 In VFG2_TRIGGER_TTL TTL 16 In VFG2_ENCODERA_TTL TTL 17 Out VFG2_GPOUT0_TTL TTL 18 Out VFG2_GPOUT1_TTL TTL 19 ...

Page 286: ... VFG1_GPIN0 38 Out VFG1_GPOUT0 LVDS 39 Out VFG1_GPOUT0 LVDS 40 In VFG1_ENCODERB_TTL TTL also VFG1_GPIN1_TTL 41 GND 42 In VFG2_ENCODERA LVDS 43 In VFG2_ENCODERA LVDS 44 In VFG2_ENCODERB LVDS also VFG2_GPIN0 45 In VFG2_ENCODERB LVDS also VFG2_GPIN0 46 Out VFG2_GPOUT0 LVDS 47 Out VFG2_GPOUT0 LVDS 48 In VFG2_ENCODERB_TTL TTL also VFG2_GPIN1_TTL 49 In VFG3_ENCODERA LVDS 50 In VFG3_ENCODERA LVDS 51 In V...

Page 287: ...CLQ I O Connector Pinout P3 Version G 5 BitFlow Inc NEO 13 21 57 Out VFG0_GPOUT2_TTL TTL 58 Out VFG1_GPOUT2_TTL TTL 59 Out VFG2_GPOUT2_TTL TTL 60 Out VFG3_GPOUT2_TTL TTL Table 13 13 P3 I O Connector Pin I O Signal Comment ...

Page 288: ...l Table 13 14 Neon DIF Main Connector Data and I O Pin I O Signal Comment 1 In CLKIN LVDS 2 In CLKIN LVDS 3 Reserved 4 In DIG8 LVDS 5 In DIG8 LVDS 6 In DIG9 LVDS 7 In DIG9 LVDS 8 In DIG10 LVDS 9 In DIG10 LVDS 10 In DIG11 LVDS 11 In DIG11 LVDS 12 In Serial Receive LVDS 13 In Serial Receive LVDS 14 In DIG12 LVDS 15 In DIG12 LVDS 16 In DIG13 LVDS 17 In DIG13 LVDS 18 In DIG14 LVDS 19 In DIG14 LVDS 20 ...

Page 289: ... Out CT2 RS422 36 Out CT2 RS422 37 Out GPOUT0 RS422 38 Out GPOUT0 RS422 39 Out GPOUT1 RS422 40 Out GPOUT1 RS422 41 Out GPOUT2 RS422 42 Out GPOUT2 RS422 43 In DIG4 LVDS 44 In DIG4 LVDS 45 In DIG5 LVDS 46 In DIG5 LVDS 47 In DIG6 LVDS 48 In DIG6 LVDS 49 In DIG7 LVDS 50 In DIG7 LVDS 51 In TRIGGER LVDS 52 In TRIGGER LVDS 53 Out Serial Transmit RS422 54 Out Serial Transmit RS422 Table 13 14 Neon DIF Mai...

Page 290: ...nout P7 The Neon NEO 13 24 BitFlow Inc Version G 5 55 GND 56 GND 57 Out CT0 RS422 58 Out CT0 RS422 59 In LEN LVDS 60 In LEN LVDS 61 In FEN LVDS 62 In FEN LVDS Table 13 14 Neon DIF Main Connector Data and I O Pin I O Signal Comment ...

Page 291: ... DIF model Table 13 15 Neon DIF Auxiliary Connector Data Pin I O Signal Comment 1 In DIG31 LVDS 2 In DIG31 LVDS 3 In DIG30 LVDS 4 In DIG30 LVDS 5 In DIG29 LVDS 6 In DIG29 LVDS 7 In DIG28 LVDS 8 In DIG28 LVDS 9 In DIG27 LVDS 10 In DIG27 LVDS 11 In DIG26 LVDS 12 In DIG26 LVDS 13 In DIG25 LVDS 14 In DIG25 LVDS 15 In DIG24 LVDS 16 In DIG24 LVDS 17 In DIG23 LVDS 18 In DIG23 LVDS 19 In DIG22 LVDS 20 In ...

Page 292: ...nout P2 The Neon NEO 13 26 BitFlow Inc Version G 5 27 In DIG18 LVDS 28 In DIG18 LVDS 29 In DIG17 LVDS 30 In DIG17 LVDS 31 In DIG16 LVDS 32 In DIG16 LVDS 33 GND 34 GND Table 13 15 Neon DIF Auxiliary Connector Data Pin I O Signal Comment ...

Page 293: ...1 Note The connector P3 is only on the NEO PCE DIF model Table 13 16 Neon I O Auxiliary Connector Pin I O Signal Comment 1 In GPIN2 ENCODER_B LVDS 2 In GPIN2 ENCODER_B LVDS 3 In TRIGGER_TTL TTL 4 In ENCODER_A_TTL TTL 5 GND 6 Out GPOUT3_TTL TTL 7 In GPIN0_TTL ENCODER_B_TTL TTL 8 Out CC4_TTL TTL 9 Out CC4 LVDS 10 Out CC4 LVDS 11 In TRIGGER LVDS 12 In TRIGGER LVDS 13 In ENCODER_A LVDS 14 In ENCODER_A...

Page 294: ...NEO PCE DIF I O Connector Pinout P3 The Neon NEO 13 28 BitFlow Inc Version G 5 ...

Page 295: ...FGDONE NEO 8 5 CFGEN NEO 8 5 CFGSTATUS NEO 8 5 CFREQ NEO 8 6 CHAIN_DATA_SIZE_HI NEO 9 9 CHAIN_DATA_SIZE_LO NEO 9 7 CHAIN_DATA_TOGO_HI NEO 9 13 CHAIN_DATA_TOGO_LO NEO 9 11 CL_DISABLE NEO 8 28 CLAST_ADD NEO 8 59 CLIP NEO 8 50 CLK_OUT_FREQ NEO 8 100 CLK_POL NEO 8 100 CMDWRITE NEO 8 20 CON0 NEO 8 4 CON1 NEO 8 8 CON10 NEO 8 52 CON11 NEO 8 56 CON12 NEO 8 58 CON13 NEO 8 60 CON14 NEO 8 62 CON15 NEO 4 6 NE...

Page 296: ...V_M NEO 8 38 ENC_DIV_N NEO 8 78 ENC_DIV_OPEN_LOOP NEO 8 72 Encoder NEO 11 4 Encoder Divider NEO 5 1 ENCPOL NEO 8 33 ENINT_CTAB NEO 8 25 ENINT_EOF NEO 8 34 ENINT_HW NEO 8 25 ENINT_OVSTEP NEO 8 25 ENINT_QUAD NEO 8 26 ENINT_SER NEO 8 26 ENINT_TRIG NEO 8 25 EOF_IN_AQ NEO 8 26 F FACTIVE NEO 8 22 FCOUNT NEO 8 22 FEN_SEL NEO 8 115 FENCOUNT NEO 8 29 FENPOL NEO 8 63 FI NEO 8 113 FI_POL NEO 8 114 NEO 8 117 ...

Page 297: ... NEO 8 91 LUT_DATA_WRITE_SEL NEO 8 91 LUT_HOST_ACCESS NEO 8 92 LUT_HOST_ADDR NEO 8 90 LUT_HOST_DATA NEO 8 90 LUT_HOST_LANE NEO 8 91 LUT_ON NEO 8 90 LUT_WEN NEO 8 91 M MEM_ADDR_LO NEO 8 102 NEO 8 104 MEM_CS NEO 8 104 MEM_DATA NEO 8 104 MEM_WRITE NEO 8 104 MID NEO 8 116 MUX_REV NEO 8 49 N NEO PCE CLB Revision 1 I O Connector Alter nate Configuration P10 NEO 13 15 NEO PCE CLB Revision 1 I O Connector...

Page 298: ..._RESET NEO 4 9 NEO 8 69 QENC_RESET_REAQ NEO 4 11 NEO 8 71 QTAB NEO 9 19 QTBSRC NEO 8 20 Quad Table NEO 9 19 R R W NEO 8 3 RD_ENC_DIFF NEO 8 34 NEO 8 35 RD_ENC_OPTO NEO 8 34 RD_ENC_TTL NEO 8 34 RD_HD NEO 8 113 RD_TRIG_DIFF NEO 8 33 RD_TRIG_OPTO NEO 8 34 RD_TRIG_TTL NEO 8 33 RD_VD NEO 8 114 RD_WEN NEO 8 113 REG_GAIN NEO 8 83 RELOAD_FPGA NEO 8 7 REV_DCC NEO 8 22 RLE_LOAD_H NEO 8 46 RLE_LOAD_V NEO 8 4...

Page 299: ...T NEO 8 30 VCNT_LD NEO 8 10 VCNT_RLS_STK NEO 8 10 VCNT_RLS_ZERO NEO 8 9 VCNT_RST NEO 8 9 VCOUNT NEO 8 38 VD_SEL NEO 8 116 Vertical Control Table Size NEO 2 15 VFG NEO 1 10 VID_BRL NEO 8 80 VID_SOURCE NEO 8 54 VIDEO_2DPM NEO 8 80 VIDEO_MASK NEO 8 61 W WO NEO 8 3 X XFR_PER_INT NEO 9 18 ...

Page 300: ...Index BitFlow Inc ...

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