B&R Industries Provit 5000, User Manual

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292 Provit 5000 User’s Manual
Software • BIOS for System Unit with Socket 370
If this option is activated, then the memory area of over 16MB cannot
be used anymore.
Passive Release
When Enabled, CPU to PCI bus accesses are permitted during the Passive
Release procedure. Otherwise, the arbiter only accepts another PCI master
access to local DRAM.
Delayed Transaction
The chipset has an embedded 32 bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
AGP Aperture Size (MB)
Identifies those memory areas which can be used as graphic memory. Write
procedures on this memory area are relayed without delay to the AGP bus.
Auto Detect DIMM/PCI Clk
The clock line is activated only with existing DIMMs.
CPU Clock (MHz) / Spread(%)
Settings of the system clock control. These values depend on the processor type.
For Celeron processors:
Default 66 MHz, -0.5% control
66(+/-.5) 66 MHz, ±0.5% control
66(-.5) 66 MHz, -0.5% control
For Pentium III 600/100:
Default 100 MHz, -0.5% control
100(+/-.5) 100 MHz, ±0.5% control
100(-.5) 100 MHz, -0.5% control
103(-.5) 103 MHz, -0.5% control
124(-.5) 124 MHz, -0.5% control
133(-.5) 133 MHz, -0.5% control