B&R Industries Provit 5000, User Manual

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Provit 5000 User’s Manual 259
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Software • BIOS System for System Units with Socket 7 (ZIF)
DRAM Timing
The value in this field depends on performance parameters of the installed
memory chips (DRAM). Do not change the value from the factory setting unless
you install new memory that has a different performance rating than the original
DRAM.
DRAM RAS# Precharge Time
The precharge time is the number of cycles it takes for the RAS to accumulate its
charge before DRAM refresh. If insufficient time is allowed, refresh may be
incomplete and the DRAM may fail to retain data.
DRAM R/W Leadoff Timing
The number of CPU tacts are defined here, which are required for every read or
write access from DRAM. Changing the value from the setting determined by the
board designer for the installed DRAM may cause memory errors.
Fast RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS to Column
Address Strobe (CAS).
DRAM Read Burst (EDO / FPM)
Sets the timing for reads from EDO (Extended Data Output) or FPM (Fast Page
Module) memory. The lower the timing value, the faster the access is in RAM.
Selecting timing values lower than the installed DRAM is able to support, can
result in memory errors.
DRAM Write Burst Timing
Sets the timing for writes to memory. The lower the timing value, the faster the
access is in RAM. Selecting timing numbers lower than the installed DRAM is able
to support can result in memory errors.
Turbo Read Leadoff
Select Enabled to shorten the leadoff cycles and optimize performance in
cacheless, 50-60 MHz, or one-bank EDO DRAM systems.