B&R Industries Provit 5000, User Manual

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Provit 5000 User’s Manual 261
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Software • BIOS System for System Units with Socket 7 (ZIF)
Peer Concurrency
"Enabled" means that more than one PCI device can be active at a time.
Chipset Special Features
When disabled, the Chipset behaves (for compatibility reasons) like an Intel
82430FX Chipset. The Intel 82430FX Chipset is the predecessor of the Intel
82430HX Chipset.
DRAM ECC/PARITY Select
This option must be set according to the type of DRAM installed in your system:
error-correcting code (ECC) or parity (default).
Memory Parity/ECC Check
Select Enabled, Disabled, or AUTO. In AUTO mode, the BIOS enables memory
checking automatically when it detects the presence of ECC or parity DRAM.
Single Bit Error Report
If this option or the Memory Parity/ECC check option is enabled, selecting
Enabled here tells the system to report an error when a correctable single-bit error
occurs.
L2 Cache Cacheable Size
This option defines those sizes of RAM, which can be read by the L2 cache.
Should always be set to 512 MB.
Chipset NA# Asserted
Selecting Enabled permits pipelining, in which the chipset signals the CPU for a
new memory address before all data transfers for the current cycle are complete,
resulting in faster performance.