B&R Industries Provit 5000, User Manual

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Provit 5000 User’s Manual 291
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Software • BIOS for System Unit with Socket 370
SDRAM CAS Latency Time
This value should not be changed as it can cause instability in the system.
SDRAM Precharge Control
This value should not be changed as it can cause instability in the system.
BIOS Cacheable
Selecting Enabled allows caching of the BIOS ROM at F0000h-FFFFFh, resulting
in better system performance. However, if any program writes to this memory
area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the Video BIOS ROM at C0000h-CBFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
Video RAM Cacheable
Selecting Enabled allows caching of the Video BIOS ROM at C0000h-CBFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
8/ 16 Bit I/O Recovery Time
The I/O recovery mechanism delays PCI I/O (created by PCI hardware), so that it
can guarantee compatibility with the ISA bus. A delay of one or more bus clock
cycles can be set. These two fields let you define recovery time (in bus clock
cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for ROM memory on ISA cards.
When this area is reserved, it cannot be cached. The user information for
peripherals that need to use this area of system memory usually describes their
memory requirements.