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Figure A-4. IIMCP01 Multibus Communication Processor
U23
SW3
LEDs
LEDs
STOP
RESET
SW4
DO1+
DO1–
P4
P5
J6
J5
J7
PORT A
PORT B
SW0
LSB
8
MSB
TP36301B
1
SW1
SW2
P6
TO IIMLM01
MSB
LSB
SW0
0 = ON OR CLOSED
1 = OFF OR OPEN
SW2
SW1
TO CPU
THROUGH
TERMINAL
SERVER
DIAGNOSTIC
PORT
DO2+
DO2–
U24
0
1
0
1
0
1
OP
E
N
1234
5678
1234
5678
1234
5678
OP
E
N
OP
E
N