Version 1.2
Zynq
®
-7000 AP SoC / Analog Devices Intelligent Drives Kit II
8
Figure 1 - Zynq Intelligent Drives Kit II Reference Design - Simplified Block Diagram
Current Monitor
- Implements the communication with the AD7403 sigma delta modulators on the AD-
FMCMOTCON2-EBZ and also the SINC3 filters for demodulating the 1-bit digital stream provided by these parts.
This HDL block exposes a set of registers that can be accessed through the AXI Lite interface. A FIFO interface
connected to a DMA controller allows the block to stream real time data to the application layer. An ADC PACK IP is
used so that 1, 2 or all channels can stream data at a time.
Motor Controller
- Implements the interface to the IP control blocks in the system. A FIFO interface connected to a
DMA controller allows the block to stream real time data to the application layer. It implements a basic six point drive
of the motor. An ADC PACK block is used so that 1, 2, 4 or all channels can stream data at a time.
Speed Detector
- Implements the algorithm for converting Hall, BEMF and Encoder signals into speed and position
data. This HDL block exposes a set of registers that can be accessed through the AXI Lite interface. A FIFO interface
connected to a DMA controller allows the block to stream real time data to the application layer.
GMII to RGMII
- Converts the GMII interface from the two Ethernet cores from the PS7 block to RGMII interface that
is available on the FMC Controller Board. The IP allows for the RX pins to be on different I/O Banks.
