AT90S8414
Preliminary
4-53
Figure 44: Sampling Received Data
When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more
samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set. Before reading the
UDR register, the user should always check the FE bit to detect Framing Errors.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the
RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received
data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is
accessed. If 9 bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR
is loaded with bit 9 in the Transmit shift register when data is transferred to UDR.
If, after having received a character, the UDR register has not been accessed since the last receive, the OverRun (OR)
flag in UCR is set. This means that the new data transferred to the shift register has overwritten the old data not yet read,
and the old data is lost. The user should always check the OR bit before reading from the UDR register in order to detect
any overruns.
By clearing the RXEN bit in the UCR register, the receiver is disabled. This means that the PD0 pin can be used as a
general I/O pin. When RXEN is set, the UART Receiver will be connected to the PD0 pin regardless of the setting of the
DDD0 bit in DDRB.
UART Control
THE UART I/O DATA REGISTER - UDR
Bit
7
6
5
4
3
2
1
0
$0C
MSB
LSB
UDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register,
the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.
THE UART STATUS REGISTER - USR
Bit
7
6
5
4
3
2
1
0
$0B
RXC
TXC
UDRE
FE
OR
-
-
-
USR
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
1
1
0
0
0
0
0
The USR register is a read-only register providing information on the UART Status.
Bit 7 - RXC: UART Receive Complete:
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set
regardless of any detected framing errors. When the RXCIE bit in UCR is set, setting of RXC causes the UART Receive
Complete interrupt to be executed. RXC is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, the bit is cleared (zero) by first reading USR while RXC is set (one) and then reading UDR.
Bit 6 - TXC : UART Transmit Complete:
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out
and no new data has been written to the UDR. This flag is especially useful in half-duplex communications interfaces,
