AT90S8414
Preliminary
4-27
Figure 28: MCU Start-Up, RESET Controlled Externally
EXTERNAL RESET
An external reset is generated by a low level on the RESET pin. The pin must be held low for at least two crystal clock
cycles. When RESET reaches the Reset Threshold Voltage - V
RST
on its positive edge, the delay timer starts the MCU
after the Time-out period t
TOUT
has expired.
Figure 29: External Reset During Operation
WATCHDOG RESET
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period t
TOUT
. Refer to Page 3-43 for details on operation of the
Watchdog.
