4-44
AT90S8414
Preliminary
Figure 37: Watchdog Timer
THE WATCHDOG TIMER CONTROL REGISTER - WDTCR
Bit
7
6
5
4
3
2
1
0
$21
-
-
-
-
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bits 7..4 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and will always read as zero.
Bit 3 - WDE : Watch Dog Enable:
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer
function is disabled.
Bits 2..0 - WDP2, WDP1, WDP0 : Watch Dog Timer Prescaler 2, 1 and 0:
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding Timeout Periods are shown in Table 12.
Table 12: Watch Dog Timer Prescale Select
WDP2
WDP1
WDP0
Timeout Period
0
0
0
16 ms
0
0
1
32 ms
0
1
0
64 ms
0
1
1
128 ms
1
0
0
256 ms
1
0
1
512 ms
1
1
0
1024 ms
1
1
1
2048 ms
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space using the IN and OUT instructions.
