4-10
AT90S8414
Preliminary
AT90S8414
AVR
RISC Microcontroller CPU
The AT90S8414
AVR
RISC microcontroller is upward compatible with the
AVR
Enhanced RISC Architecture. The
programs written for the AT90S8414 MCU are fully compatible with the range of
AVR
8-bit MCUs (AT90Sxxxx) with
respect to source code and clock cycles for execution.
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is executed, and the result is stored back in the register file - in
one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for SRAM addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 4: The AT90S8414
AVR
Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the AT90S8414
AVR
Enhanced RISC microcontroller
architecture.
