AT90S8414
Preliminary
4-31
INTERRUPT RESPONSE TIME
The interrupt response time for all the enabled
AVR
interrupt is 4 clock cycles. After the 4 clock cycles the program
vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter
(2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. A return from an interrupt handling routine
(same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes) is
popped back from the Stack, and the Stack Pointer is incremented by 2.
Note that the Status Register - SREG - is not handled by the
AVR
hardware, neither for interrupts nor for subroutines.
For the interrupt handling routines requiring a storage of the SREG, this must be performed by user software.
For Interrupts triggered by events that can remain static (E.g. the Output Compare register0 matching the value of
Timer/Counter0) the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition
persists, the flag will not be set until the event occurs the next time.
MCU CONTROL REGISTER - MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
5
4
3
2
1
0
$35
SRE
SRW
SE
SM
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit 7 - SRE : External SRAM Enable:
When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions AD0-7 (Port A), A8-15 (Port C),
WR and RD (Port D) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings
in the respective data direction registers. See “
