4-40
AT90S8414
Preliminary
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 -
on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are
transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
Bits 5, 4 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and always read zero.
Bit 3 - CTC1 : Clear Timer/Counter1 on Compare match:
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match.
If the CTC1 control bit is cleared, the Timer/Counter1 continues counting until it is stopped, cleared, wraps around
(overflow) or changes direction. In PWM mode, this bit has no effect.
Bits 2,1,0 - CS12, CS11, CS10 : Clock Select1, bit 2,1 and 0:
The Clock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1.
Table 9: Clock 1 Prescale Select
CS12
CS11
CS10
Description
0
0
0
Stop, the Timer/Counter1 is stopped.
0
0
1
CK
0
1
0
CK / 8
0
1
1
CK / 64
1
0
0
CK / 256
1
0
1
CK / 1024
1
1
0
External Pin T1, rising edge
1
1
1
External Pin T1, falling edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the
CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual direction
control register (cleared to zero gives an input pin).
THE TIMER/COUNTER1 - TCNT1H AND TCNT1L
Bit
15
14
13
12
11
10
9
8
$2D
MSB
TCNT1H
$2C
LSB
TCNT1L
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary register (TEMP).
·
TCNT1 Timer/Counter1 Write:
When the CPU writes to the low byte TCNT1L, the written data is placed in the TEMP register. Next, when the CPU
writes the high byte TCNT1H, this byte of data is combined with the byte data in the TEMP register, and all 16 bits
are written in the TCNT1 Timer/Counter1 register simultaneously. Consequently, the low byte TCNT1L must be
accessed first for a full 16-bit register write operation.
·
TCNT1 Timer/Counter1 Read:
