AT90S8414
Preliminary
4-11
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost SRAM addresses, allowing them to be
accessed as though they were ordinary memory locations.
The
AVR
uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-
fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 4K address space is directly accessed. All
AVR
instructions have a
single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts
are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.
The 256 bytes data SRAM can be easily accessed through the four different addressing modes supported in the
AVR
architecture.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The memory spaces in the
AVR
architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the
status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of
the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower
the interrupt address vector the higher priority.
