Atec gigaBERT1400, User Manual

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Functional Overview
2-26 GB1400 User Manual
Burst Mode Option
The standard GB1400 operates over a clock frequency range of 1 Mbit/s to 1400
Mbit/s. The GB1400 Tx has an internal clock source that has a range of 1 MHz to
1400 MHz. It also has a provision for using an external clock source of the same
frequency range. When using the external clock source, it must be applied
continuously without interruption. The GB1400 RX also requires that, at all
times during the test, a clock signal within the 1 Mbit/s to 1400 Mbit/s frequency
range be continuously applied. If the external clock signal should be removed , or
go below 1 MHz for any reason during the test, the RX will register OUT OF
SYNC as soon as the clock signal is reapplied. This condition will initiate a
resynchronization of the receiver and restart any tests.
For the Burst Mode option, the GB1400 RX has been modified to work normally
or in Burst Mode from 150 kHz to the normal 1400 MHz upper limit. The RX
CLOCK and CLOCK BAR inputs have been modified for DC operation. This
modification requires the removal of any blocking capacitors in the input path.
The removal of the capacitors limits the allowable input signal to ECL levels
only. Levels other than ECL may damage the input circuitry. The three standard
clock input termination selections of GND, AC, and -2V are still present.
Note: The Clock may be used either differentially or single-ended. To use a
single-ended clock input, connect the ECL clock input to the CLOCK input
connector. Select the -2V input termination, and connect DC bias voltage of -1.3
VDC to the CLOCK BAR input connector.
These and other changes will now allow the receiver to maintain synchronization
whenever CLOCK and DATA are synchronously stopped and started during a
test pattern, providing there has not been a bit slip between CLOCK and DATA.
In both the Tx and RX, there can be any length of time that both CLOCK and
DATA are off, and the minimum CLOCK/DATA applied can be as low as a
single cycle, providing the minimum of 714 pS and maximum of 667
µ
s clock
period restrictions are observed.
Similar Tx circuit changes allow the Tx DATA and CLOCK outputs to follow,
cycle by cycle, the input from a bursted External Clock Input. This means that
the Tx can be used in a start-stop, or "Burst Mode".
For every clock cycle into the External Clock Input, there will be the same
number of clock cycles and data bits output through the clock and data outputs.
The time between clock cycle inputs is unrestricted and can be any length of
time. The number of clock cycles can be any number from continuous to a single
cycle. During the time there is no clock input to the External Clock Input, the
internal code generator is idle (not running). Each clock cycle steps the code
generator by one bit. Clock cycle period must not be more than 667
µ
s (150
kHz) nor less than 714 pS (1400 MHz).