Artesyn SharpSwitch PCIE-9205, Additional Information For The Installation And Use

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Controls, Indicators, and Connectors
SharpSwitch™ PCIE-9205 Installation and Use (6806800U18D )
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4 GND Ground GND Ground
5 SMCLK PCIE EDGE SMBCLK SMBus
(System Management Bus)
Clock JTAG2 PCIe Edge Test Clock (TCK)
6 SMDAT PCIE EDGE SMBDAT SMBus
(System Management Bus)
Data JTAG3 PCIe Edge Test Data Input
(TDI)
7 GND Ground JTAG4 PCIe Edge Test Data Output
(TDO)
8 +3.3V 3.3 Volt power JTAG5 PCIe Edge Test Mode Select
(TMS)
9 JTAG1 PCIE EDGE TRST L
TRST# (Test Reset) resets
the JTAG interface +3.3V 3.3 Volt power
10 3.3V AUX 3.3 Volt auxiliary power +3.3V 3.3 Volt power
11 WAKE# Signal for Link reactivation PRST# Reset
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground Reference clock
14 Tx_P(0) Transmitter Lane 0 REFCLK- Differential pair
15 Tx_N(0) Differential pair GND Ground
16 GND Ground Rx_P(0) Receiver Lane 0
17 PRSNT2# Hot-Plug presence detect Rx_N(0) Differential pair
18 GND Ground GND Ground
19 Tx_P(1) Transmitter Lane 1 RSVD Reserved
20 Tx_N(1) Differential pair GND Ground
21 GND Ground Rx_P(1) Receiver Lane 1
22 GND Ground Rx_N(1) Differential pair
23 Tx_P(2) Transmitter Lane 2 GND Ground
Table 3-1 PCIE-9205 Card Edge Connector 1 Pinout (continued)
Pin #
Name
Side B Description Name Side A Description