DECA User Manual
18
www.terasic.com
May 22, 2015
Figure 3-10 Block diagram of the clock distribution on DECA
Table 3-2 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
MAX10_CLK1_50
PIN_M8
50 MHz clock input
2.5V
MAX10_CLK2_50
PIN_P11
50 MHz clock input
3.3V
DDR3_CLK_50
PIN_N15
50 MHz clock input
1.5V
ADC_CLK_10
PIN_M9
10 MHz clock input
2.5V
3
3
.
.
4
4
P
P
e
e
r
r
i
i
p
p
h
h
e
e
r
r
a
a
l
l
s
s
C
C
o
o
n
n
n
n
e
e
c
c
t
t
e
e
d
d
t
t
o
o
t
t
h
h
e
e
F
F
P
P
G
G
A
A
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.
