DECA User Manual
23
www.terasic.com
May 22, 2015
Figure 3-16 Connections between the power monitor chip and the MAX 10 FPGA
Table 3-7 Pin Assignment of Power Monitor I2C bus
Signal Name
FPGA Pin No.
Description
I/O Standard
PMONITOR_I2C_SCL PIN_Y3
Power Monitor SCL
3.3V
PMONITOR_I2C_SDA PIN_Y1
Power Monitor SDA
3.3V
PMONITOR_ALERT
PIN_Y4
Power Monitor ALERT
3.3V
3
3
.
.
4
4
.
.
3
3
T
T
w
w
o
o
2
2
x
x
2
2
3
3
E
E
x
x
p
p
a
a
n
n
s
s
i
i
o
o
n
n
H
H
e
e
a
a
d
d
e
e
r
r
s
s
The board has two 46-pin expansion headers. The P8 header has 44 digital user pins connected
directly to the MAX 10 FPGA, the P9 header has 25 digital and 7 analog user pins connected to the
MAX 10 FPGA. The P9 header also comes with DC +5V (VCC5), DC +3.3V (VCC3P3) power
pins. The maximum power consumption allowed for a daughter card connected to one or two GPIO
ports is shown in
Table 3-8
.
Table 3-8 Voltage and Max. Current Limit of Expansion Header(s)
Supplied Voltage
Max. Current Limit
5V
1A
3.3V
1A
