DECA User Manual
88
www.terasic.com
May 22, 2015
controller. The DDR3 IP generates one 300 MHz clock as SDRAM’s data clock and one half-rate
system clock 150 MHz for those host controllers, e.g. Nios II processor, accessing the SDRAM. In
the QSYS, Nios II and the On-Chip Memory are designed running with the 125 MHz clock, and the
Nios II program is running in the on-chip memory.
Figure 6-16 Block diagram of the DDR3 Basic Demonstration
The system flow is controlled by a Nios II program. First, the Nios II program writes test patterns
into the whole 512 MB of SDRAM. Then, it calls Nios II system function, alt_dache_flush_all, to
make sure all data has been written to SDRAM. Finally, it reads data from SDRAM for data
verification. The program will show progress in JTAG-Terminal when writing/reading data to/from
the SDRAM. When verification process is completed, the result is displayed in the JTAG-Terminal.
Altera DDR3 SDRAM Controller with UniPHY
To use Altera DDR3 controller, users need to perform the four major steps:
1.
Create correct pin assignments for DDR3.
2.
Setup correct parameters in DDR3 controller dialog.
3.
Perform “Analysis and Synthesis” by clicking Quartus menu: Process
Start
Start
Analysis & Synthesis.
4.
Run the TCL files generated by DDR3 IP by clicking Quartus menu: Tools
TCL Scripts…
Design Tools
