H A R D W A R E D E S C R I P T I O N
DNPCIe_10G_K7_LL (_QSFP) User Manual
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The RESET and CKE signals are not terminated. These signals should be
pulled down during memory initialization with a 4.7 kΩ resistor connected to
GND.
ODT, which terminates a signal at the memory, and DCI, which terminates a
signal at the FPGA, are required. The MIG tool should be used to specify the
configuration of the memory system for setting the mode register properly.
Refer to Micron technical note TN-47-01 for additional details on ODT.
ODT applies to the DQ, DQS, and DM signals only. If ODT is used, the mode
register must be set appropriately to enable ODT at the memory.
2.4.3
Design Guidelines
–
DDR3 IO Standards
These rules apply to the I/O standard selection for DDR3 SDRAMs:
Designs generated by the MIG tool use the SSTL15_T_DCI and
DIFF_SSTL15_T_DCI standards for all bidirectional I/O (DQ, DQS).
The SSTL15 and DIFF_SSTL15 standards are used for unidirectional outputs,
such as control/address, and forward memory clocks.
The MIG tool creates the UCF using the appropriate standard based on input from the
GUI.
2.4.4
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with
JEDEC Standard JC-45, “Appendix X: Serial Presence-Detect (SPD) for DDR3
SDRAM Modules.” These bytes identify module-specific timing parameters,
configuration information, and physical attributes. User-specific information can be
written into the remaining 128 bytes of storage. READ/WRITE operations between the
system (master) and the EEPROM (slave) device occur via a standard I2C bus using the
DIMM’s SCL (clock) and SDA (data) signals, together with SA[1:0], which provide four
unique DIMM/EEPROM addresses. Write protect (WP) is connected to Vss internal to
the Temp Sensor/EEPROM, permanently disabling hardware write protection. Please
note that VDDSPD is connected to +3.3V.
Table 6 - Serial Presence-Detect EEPROM Connections
Signal Name
FPGA
MINIUDIMM
DIMM_SA0
NC
J7-119, pull-down 4.7K (R256)
DIMM_SA1
NC
J7-241, pull-down 4.7K (R323)
DIMM_SA2
NC
J7-121, pull-down 4.7K (R255)
DIMM_SCL
U6-E12
J7-120 pull-up 4.7K (R285)
