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P R O G R A M M I N G / C O N F I G U R I N G   T H E   H A R D W A R E  

DNPCIe_10G_K7_LL (_QSFP) User Manual             

www.dinigroup.com

                             22 

 

Following the Vivado build flow for the Darklite reference design a post-routing dcp file 

is saved under implement directory. Depending on your build, the dcp file can be either 
for the golden image (needs to be generated only once) or for the update image. You 

can run the following TCL commands in Vivado once you change directory to Darklite 

build 

directory 

(usually 

“FPGA 

Reference 

Designs/boards/dn0###_.../darklite/build/implement”; NB: DCP file names are for 
illustrative purposes only, your file names may vary): 

close_project 
open_checkpoint checkpoint_3_post_route_golden.dcp 
source bitgenoptions_golden.tcl 
write_bitstream -force fpga_golden.bit 
write_cfgmem  -force  -interface  bpix16  -format  MCS  -size  128  -
loadbit "up 0x00000000 fpga_golden.bit"  fpga_golden.mcs 
 
close_project 
open_checkpoint checkpoint_3_post_route_update.dcp 
source bitgenoptions_update.tcl 
write_bitstream -force fpga_update.bit 
write_cfgmem  -force  -interface  bpix16  -format  MCS  -size  128  -
loadbit "up 0x01000000 fpga_update.bit"  fpga_update.mcs

  

 

The above commands assume that the golden image is stored in flash at word address 
0x0, and update image is stored in flash at word address 0x01000000. Because the flash 

is BPIx16, this corresponds to a byte address of 0x02000000. This byte offset must be 

larger than the size of the golden image (.bit file) in bytes. This offset is appropriate if the 

golden image is the Darklite image provided with the board. 

Golden and update MCS files can be written to flash using Vivado. Alternatively, one 

can use aetest software to write corresponding golden and update .bit images to flash: 

./aetest_linux -cfpga=fpga_golden.bit,0x0 
./aetest_linux -cfpga=fpga_update.bit,0x2000000 
 

Notice that the offset provided to aetest command is a byte offset (rather than a word 

offset).  Also  notice  that  BPI  flash  has  256KB  block  size  so  you  want  to  set 
NEXT_CONFIG_ADDR  in  bitgen  TCL  files  such  that  offset  falls  on  a  block 

boundary. 

4

 

Using ChipScope Pro (via JTAG) 

The Xilinx ChipScope Pro tool inserts logic analyzer, system analyzer, and virtual I/O 

low-profile software cores directly into the design, allowing the user to view any internal 
signal or node, including embedded hard or soft processors. Signals are captured in the 

Summary of Contents for DNPCIe 10G K7 LL QSFP

Page 1: ...DINI GROUP LOGIC Emulation Source UserManual DNPCIe_10G_K7_LL _QSFP ...

Page 2: ...T I O N SO UR C E DNPCIe_10G_K7_LL _QSFP User Manual Version 1 9 DateofPrintDecember12 2017 Dini Group 2012 2017 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com ...

Page 3: ...ation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However the Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss...

Page 4: ...E SOFTWARE 8 2 1 Exploring the Customer Support Package 9 3 BOARD SETUP 9 3 1 Before Powering Up the Board 9 3 2 Cooling Requirements IMPORTANT 10 3 3 Powering Up the Board 10 4 USING THE REFERENCE DESIGN MAIN 11 PROGRAMMING CONFIGURING THE HARDWARE 14 1 INTRODUCTION 14 2 CONFIGURING THE FPGA USING JTAG 15 2 1 Setup Configuring the FPGA using JTAG 15 2 2 Powering Up the Board 15 2 3 Installing Dig...

Page 5: ... 41 2 5 1 EEPROM Circuit Diagram 41 2 5 2 Connections between FPGA and the EEPROM 41 2 6 PCI Express Interface x4 41 2 6 1 System Requirements 42 2 6 2 Clocking Jitter Attenuator 42 2 6 3 PCI Express Circuit 42 2 6 4 Connections between FPGA and PCI Express Edge Connector 42 2 7 SFP Interface only for DNPCIe_10G_K7_LL 43 2 7 1 SFP Circuit Diagram 43 2 7 2 LED indicators 44 2 7 3 SFP Pin Assignment...

Page 6: ...rive Directory Structure 9 Figure 3 DNPCIe_10G_K7_LL _QSFP Block Diagram Note the two SFP modules are replaced with one QSFP module in the _QSFP version 26 Figure 4 FPGA Serial Port 29 Figure 5 QDR II Memory Architecture 30 Figure 6 FPGA Serial Port 41 Figure 7 SFP Channel 0 Interface 44 Figure 8 SFP GTX Oscillator 44 Figure 9 QSFP Channel 0 Interface 47 Figure 10 QSFP GTX Oscillator 48 ...

Page 7: ...ctions between FPGA and the UDIMM Connector 36 Table 8 Connections between FPGA and the UDIMM Connector 36 Table 9 Connections between FPGA and the EEPROM 41 Table 10 Connections between FPGA and the PCI Express Edge Connector 43 Table 11 SFP Pin Assignments 45 Table 12 Connections between FPGA and the SFP Connectors 46 Table 13 QSFP Pin Assignments 48 Table 14 Connections between FPGA and the QSF...

Page 8: ...are computing platform has the ability to achieve the theoretical minimum Ethernet packet processing latency This board also has a time code input to allow for precise message time stamping and tracking 1 2 FPGA Xilinx Kintex 7 The Xilinx Kintex 7 in the FFG676 package is utilized for this product This package supports 400 IOs with the majority utilized Most are dedicated to a variety of off chip ...

Page 9: ...ricky re synchronization of data moving between different clock frequencies The internal controller can be optimized in any way you choose Dini Group provides several Verilog examples All functions of the QDR II SSRAM can be exploited including concurrent read and write operations and four tick bursts The only real limitation is the amount of time and effort spent in customizing the individual mem...

Page 10: ...C source for drivers for several operating systems are included no charge Partial reconfiguration of the FPGA is supported via the PCIe interface 1 7 Time Synchronization The time code input allows for precise message time stamping and tracking This input can receiver PPS or IRIG B000 RS232 RS485 RS422 TLL 1 8 How Everything Works With direct data feeds such as NASDAQ ITCH OUCH or Financial Inform...

Page 11: ..._LL and lower picture is the DNPCIe_10G_K7_LL_QSFP DNPCIe_10G_K7_LL _QSFP Kintex 7 Board features the following Hosted in a 4 lane 16 lane mechanical with notches to allow to be plugged into x4 x8 x16 PCI Express Slot GEN2 or Stand alone Xilinx Kintex 7 FPGA FFG676 o XC7K325T 3 2 1 fastest to slowest o XC7K410T 3 2 1 fastest to slowest GTX Transceivers 10Gb s o PCI Express x4 o Two SFP modules x1 ...

Page 12: ...ation DDR double data rate Fast enough to be clocked at 312 50 MHz Eliminates clock synchronization delays between memory and Ethernet clock User LED s Time Synchronization o 2 5mm jack that accepts PPS and IRIG B000 RS232 RS485 RS422 TTL time code Onboard Distributed Power Supplies Full support for Embedded Logic Analyzers and Debug o ChipScope Logic Analyzer o InPA Veridae SpringSoft USB B 2 0 P...

Page 13: ...following USB Flash Drive 4GB USB007 P N UFDCR 4096 USB 2 0 Cable NewEgg P N N82E16812119030 VLP MINIUDIMM DDR3 2GB PC3 10600 244 Pin Micron P N MT9JBG25672AKZ 1G4 DB9 to 2 5mm cable P N BC20223 6 Customer Support Package on USB Flash Drive o Documentation Datasheets User Manual and Schematics o FPGA Reference Designs Verilog o Host Software AETest Cooling Requirements for DNPCIE_10G_K7_LL pdf Opt...

Page 14: ...d removal video Dini Group Web Site The web page will contain the latest user manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from 7 Series Databook which contains device specific information on Xilinx device characteristics E Mail You may direct questions and feedback to Dini Group using this e mail ad...

Page 15: ...ot need to alter any jumpers or program anything to see the board work 1 2 Warnings Mechanical Stress Inserting and removing VLP MINIUDIMM and the board from the motherboard can add additional stress that may cause board failures ESD Warning The board is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and c...

Page 16: ...f Contents Documentation Contains the Datasheets Schematics and User Manual for the board FPGA Reference Designs Contains the source and compiled programming files for the DNPCIe_10G_K7_LL _QSFP reference designs Host Software Provides the Host Software for the Windows and Linux platforms 3 Board Setup The instructions in this section explain how to install the DNPCIe_10G_K7_LL _QSFP Ethernet Pack...

Page 17: ...lternatively the automatic power down can be enabled by using a configuration option in the ISE design tools To generate a programming file the user checks the Power Down Device if Over Safe Temperature option under Configuration Options on the Process Properties GUI Either of these options default to 125C being the Over Temperature threshold 2 Set user defined thresholds in the control registers ...

Page 18: ...Emulator and configure the session as follows 4 Using the Reference Design Main This section lists detailed instructions for executing the reference design Ensure the DNPCIe_10G_K7_LL _QSFP Ethernet Packet Analysis Engine is powered ON and a Terminal Window is open to exercise the reference design options 1 Select test option 6 Clock Frequencies Check in the Terminal window and verify that the tes...

Page 19: ... that the test PASS periods will be displayed as the memory locations are being tested if no DDR3 Module is present the test will display read write errors 3 Select test option 3 QDR2 Test in the Terminal window and verify that the test PASS periods will be displayed as the memory locations are being tested if no QDR2 Memory fails the test will display read write errors ...

Page 20: ...the reference design functional tests requires various loop back test boards modules to make them PASS and is not covered in this User Manual Please reference the Customer Support Package on USB Flash Drive for code examples The next section describes configuring and programming the hardware in detail ...

Page 21: ... configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration...

Page 22: ...lling Digilent cable driver JTAG access to FPGA via USB is provided using the Digilent cable driver 2 3 1 Windows For ISE 14 7 version of tools selecting cable driver installation during setup installs the Digilent driver by default and no further modifications are needed For Vivado 2014 3 version of tools selecting cable driver installation during setup does not copy libCseDigilent dll to the app...

Page 23: ... avoid the notification about windrvr6 when the tools cannot find any cable driver Make sure to source opt Xilinx 14 7 LabTools settings32 64 c sh If after completing step 3 the following file etc ld so conf d digilent adept libraries conf does not exist then re run the install_digilent sh script Vivado 2014 3 installs correctly the Digilent cable driver during setup when install cable drivers is ...

Page 24: ...nfigure devices using Boundary Scan JTAG from the iMPACT welcome menu 2 iMPACT will identify the components in the JTAG chain A pop up window will display ERROR iMPACT Bsdl reader is not available for device 3 Click OK to proceed Reason QDR2 devices are also in the JTAG chain 3 A pop up window will display Device Programming Properties Device 1 Programming Properties Click OK to select default opt...

Page 25: ...uccessful configuration of the FPGA 3 Configuring the FPGA using Master BPI In Master Byte wide Peripheral Interface BPI Mode the Kintex 7 FPGA configures itself from an attached industry standard parallel NOR flash PROM The board is populated with a Micron 1 Gbit Flash PROM part IDs MT28GU01GAAA1EGC 0SIT or PC28F00AP30BFA Table 2 shows the uncompressed configuration file size for the supported Ki...

Page 26: ...D DS16 is ON indicating the presence of 12V located on the back side of the board near the top left 3 3 Configuring the FPGA To configure the Xilinx FPGA perform the following steps 1 Open iMPACT and create a new default project Select Configure devices using Boundary Scan JTAG from the iMPACT welcome menu 2 iMPACT will identify the components in the JTAG chain A pop up window will display ERROR i...

Page 27: ...OM file based on the type of FPGA populated e g XC7K325T 5 Select the 28F00AG18F or 28F00AP30B device in the Select Attached SPI BPI window Use the former part first it was announced EOL 2017 so newer boards may be stuffed with the second part and if that fails use the latter part 6 Right Click on the FLASH icon and select Program Uncheck the Verify checkbox followed by OK A Process Dialog box wil...

Page 28: ... the start of fabric configuration bits let s call this a header has a next address that points to the flash start address of the update image Once the configuration state machine reads this next address in the golden image header it goes to the flash address corresponding to the update image and starts reading configuration header and fabric bits from there Both images contain a timer instruction...

Page 29: ... size 128 loadbit up 0x01000000 fpga_update bit fpga_update mcs The above commands assume that the golden image is stored in flash at word address 0x0 and update image is stored in flash at word address 0x01000000 Because the flash is BPIx16 this corresponds to a byte address of 0x02000000 This byte offset must be larger than the size of the golden image bit file in bytes This offset is appropriat...

Page 30: ...Connect the USB 2 0 Cable to the bracket mounted USB 2 0 B connector 4 2 Powering Up the Board 1 Power up the board by turning ON the ATX power supply to the motherboard and verify the 12V LED DS16 is ON indicating the presence of 12V located on the back side of the board near the top left 4 3 Configuring the FPGA To configure the Xilinx FPGA perform the following steps Note Non Xilinx devices in ...

Page 31: ... H E H A R D W A R E DNPCIe_10G_K7_LL _QSFP User Manual www dinigroup com 24 Note In order for the JTAG offsets to be set correctly set the IR Length for the QDR SRAMs to 3 2 Proceed as normal see UG029 ChipScope Pro Software and Cores User Guide ...

Page 32: ...ication is for ultra low latency high throughput trading without CPU intervention Every possible variable that affects input to output latency has been analyzed and minimized Raw 10 GbE Ethernet packets can be analyzed and acted upon without interrupts or an operating system adding delay to the process This configurable hardware computing platform has the ability to achieve the theoretical minimum...

Page 33: ...andling data rates of 500 MB s to 12 5 Gb s making these applicable to 10 Gigabit Ethernet 10 GbE and GEN1 GEN2 PCI Express applications Four of the GTX transceivers are used for GEN2 capable PCIe For the DNPCIe_10G_K7_LL version two of the GTX transceivers are connected to 10 GbE SFP sockets For the DNPCIe_10G_K7_LL_QSFP version four of the GTX transceivers are connected to the 40 GbE QSFP socket...

Page 34: ...sing a 2 or 3 speed grade FPGA this interface is tested at the maximum FPGA I O frequency 666 5MHz 1333Mb s with DDR The user can use this memory as 64 bits with 8 bits of error correction ECC or as a 72 bit byte memory without correction To minimize data synchronization across clock boundaries it probably makes sense to clock the DDR3 interface at a 3x multiple of the base Ethernet frequency of 1...

Page 35: ...configuration modes The following configuration modes are supported Master BPI x16 JTAG Boundary Scan The FPGA drives up to 26 address lines to access the attached parallel flash For configuration from industry standard parallel NOR flash only asynchronous read mode is used In asynchronous read mode the FPGA drives the address bus and the flash PROM drives back the bitstream data Using the JTAG in...

Page 36: ...ecture Similar to QDR II architecture QDR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around ...

Page 37: ...lanatory wizard tool that can be invoked under the CORE Generator software Xilinx published a memory application note please refer to UG 586 7 Series FPGAs Memory Interface Solutions User Guide Figure 5 QDR II Memory Architecture The memory is also mapped into the JTAG chain and is fully compliant with IEEE Standard 1149 1 2001 2 3 2 Design Guidelines QDR II SRAM IO Standards The MIG tool generate...

Page 38: ...QDR II SRAM Devices Signal Name FPGA QRD II SRAM QDRIIP_BWS0n U6 AA25 U4 B7 QDRIIP_BWS1n U6 AB25 U4 A5 QDRIIP_CQ U6 N21 U4 A11 QDRIIP_CQn U6 R21 U4 A1 QDRIIP_D0 U6 V21 U4 P10 QDRIIP_D1 U6 V22 U4 N11 QDRIIP_D2 U6 U22 U4 M11 QDRIIP_D3 U6 U24 U4 K10 QDRIIP_D4 U6 U25 U4 J11 QDRIIP_D5 U6 W25 U4 G11 QDRIIP_D6 U6 V26 U4 E10 QDRIIP_D7 U6 W26 U4 D11 QDRIIP_D8 U6 U26 U4 C11 QDRIIP_D9 U6 AC26 U4 B3 QDRIIP_D1...

Page 39: ...QDRIIP_Q6 U6 M22 U4 E11 QDRIIP_Q7 U6 M24 U4 C10 QDRIIP_Q8 U6 L24 U4 B11 QDRIIP_Q9 U6 T24 U4 B2 QDRIIP_Q10 U6 T25 U4 D3 QDRIIP_Q11 U6 T23 U4 E3 QDRIIP_Q12 U6 R23 U4 F2 QDRIIP_Q13 U6 T22 U4 G3 QDRIIP_Q14 U6 R22 U4 K3 QDRIIP_Q15 U6 U19 U4 L2 QDRIIP_Q16 U6 T20 U4 N3 QDRIIP_Q17 U6 R20 U4 P3 QDRIIP_QVLD U6 P21 U4 P6 QDRIIP_RPSn U6 AE22 U4 A8 QDRIIP_WPSn U6 AE25 U4 A4 QDRIIP_SA0 U6 AD25 U4 A3 QDRIIP_SA1 ...

Page 40: ...2 1866Mb s Speed Grade 1 1600Mb s The VLP MINIUDIMM interface is connected to IO Banks on the Kintex 7 FPGAs and uses a 1 5V switching power supply for VDD and VCCIO VTT and VREF are powered from a separate linear power supply set at 0 75V DDR3 SDRAM modules are available from Micron example part number for a 2GB 256Mbx72 244 pin VLP MINIUDIMM SDRAM module is MT9JBG25672AKZ 1G4 2 4 1 DDR3 SDRAM Me...

Page 41: ...on is needed at both ends of the signal DCI ODT or external termination Differential signals should be terminated with the memory device s internal termination or a 80Ω differential termination at the load For bidirectional signals termination is needed at both ends of the signal DCI ODT or external termination All termination must be placed as close to the load as possible The termination can be ...

Page 42: ...ard memory clocks The MIG tool creates the UCF using the appropriate standard based on input from the GUI 2 4 4 Serial Presence Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence detect The SPD data is stored in a 256 byte EEPROM The first 128 bytes are programmed by Micron to comply with JEDEC Standard JC 45 Appendix X Serial Presence Detect SPD for DDR3 SDRAM Modules These by...

Page 43: ... J7 187 DIMM_CK1P U6 AB12 J7 64 DIMM_CK1N U6 AC12 J7 65 2 4 6 Connections between FPGA and MINIUDIMM Table 8 shows the connections between the FPGA and the MINIUDIMM connector pins Table 8 Connections between FPGA and the UDIMM Connector Signal Name FPGA UDIMM DIMM_A0 U6 AA10 J7 191 DIMM_A1 U6 AB10 J7 184 DIMM_A2 U6 AC13 J7 62 DIMM_A3 U6 AB7 J7 183 DIMM_A4 U6 AB9 J7 60 DIMM_A5 U6 AA8 J7 59 DIMM_A6...

Page 44: ...B5 U6 Y8 J7 162 DIMM_CB6 U6 Y7 J7 167 DIMM_CB7 U6 V7 J7 168 DIMM_CK0P U6 AE12 J7 186 DIMM_CK0N U6 AF12 J7 187 DIMM_CK1P U6 AB12 J7 64 DIMM_CK1N U6 AC12 J7 65 DIMM_CKE0 U6 AD11 J7 51 DIMM_CKE1 U6 AA13 J7 172 DIMM_DM0 U6 AE15 J7 128 DIMM_DM1 U6 AC14 J7 137 DIMM_DM2 U6 AC19 J7 146 DIMM_DM3 U6 V16 J7 155 DIMM_DM4 U6 U6 J7 207 DIMM_DM5 U6 Y3 J7 216 DIMM_DM6 U6 AC6 J7 225 DIMM_DM7 U6 AE1 J7 234 DIMM_DM8...

Page 45: ...DQ14 U6 AB14 J7 140 DIMM_DQ15 U6 AA14 J7 141 DIMM_DQ16 U6 AB19 J7 22 DIMM_DQ17 U6 AA20 J7 23 DIMM_DQ18 U6 AD19 J7 28 DIMM_DQ19 U6 AD18 J7 29 DIMM_DQ20 U6 AC18 J7 143 DIMM_DQ21 U6 AC17 J7 144 DIMM_DQ22 U6 AB17 J7 149 DIMM_DQ23 U6 AA19 J7 150 DIMM_DQ24 U6 V18 J7 31 DIMM_DQ25 U6 V19 J7 32 DIMM_DQ26 U6 Y17 J7 37 DIMM_DQ27 U6 V17 J7 38 DIMM_DQ28 U6 W15 J7 152 DIMM_DQ29 U6 W16 J7 153 DIMM_DQ30 U6 V14 J7...

Page 46: ...AA3 J7 219 DIMM_DQ47 U6 W1 J7 220 DIMM_DQ48 U6 AA4 J7 101 DIMM_DQ49 U6 AB4 J7 102 DIMM_DQ50 U6 Y6 J7 107 DIMM_DQ51 U6 AB6 J7 108 DIMM_DQ52 U6 AC3 J7 222 DIMM_DQ53 U6 AC4 J7 223 DIMM_DQ54 U6 AD6 J7 228 DIMM_DQ55 U6 Y5 J7 229 DIMM_DQ56 U6 AE3 J7 110 DIMM_DQ57 U6 AD4 J7 111 DIMM_DQ58 U6 AE6 J7 116 DIMM_DQ59 U6 AE5 J7 117 DIMM_DQ60 U6 AD1 J7 231 DIMM_DQ61 U6 AF2 J7 232 DIMM_DQ62 U6 AF3 J7 237 DIMM_DQ6...

Page 47: ..._DQS6P U6 AA5 J7 105 DIMM_DQS7N U6 AF4 J7 113 DIMM_DQS7P U6 AF5 J7 114 DIMM_DQS8N U6 W9 J7 43 DIMM_DQS8P U6 W10 J7 44 DIMM_EVENTN U6 AC16 J7 190 DIMM_NC1 U6 AC2 J7 49 DIMM_NC2 U6 AD5 J7 54 DIMM_NC3 U6 U9 J7 69 DIMM_NC4 U6 Y13 J7 81 DIMM_NC5 U6 V12 J7 170 DIMM_NC6 U6 V13 J7 171 DIMM_NC7 U6 W13 J7 202 DIMM_ODT0 U6 AE8 J7 198 DIMM_ODT1 U6 AE10 J7 78 DIMM_RASN U6 AD10 J7 195 DIMM_WEN U6 AF13 J7 74 DIM...

Page 48: ...apped to 0000000x where x is the R W bit The eighth bit of the device address is the read write operation select bit A read operation is initiated if this bit is HIGH and a write operation is initiated if this bit is LOW 2 5 2 Connections between FPGA and the EEPROM The connections between the FPGA and the EEPROM are shown in Table 9 Table 9 Connections between FPGA and the EEPROM Signal Name FPGA...

Page 49: ... Service Pack ISE software Service Packs can be downloaded from http www xilinx com support download index htm For more information regarding the Kintex 7 FPGA Integrated Block for PCI Express reference the PG054 7 Series FPGAs Integrated Block for PCI Express Product Guide 2 6 2 Clocking Jitter Attenuator The ICS874001AGI 02LF U9 is a high performance Differential to LVDS Jitter Attenuator design...

Page 50: ...nly for DNPCIe_10G_K7_LL The 10GBASE SFP modules offer customers a wide variety of 10 Gigabit Ethernet connectivity options for data center enterprise wiring closet and service provider transport applications SFP is defined as Small Form Factor Pluggable standard by the SFP MSA and is most commonly used for 10 Gigabit Ethernet or 10 Gigabit Fiber Channel applications The SFP modules are hot plugga...

Page 51: ...ies P N 534SC000390DG The oscillator power supply is filtered to reduce power supply noise and jitter Figure 8 SFP GTX Oscillator 2 7 2 LED indicators SFP0 and SFP1 have separate LED indicators that indicate the state to the light pipes that display on the bracket On the bracket 0 indicated SFP0 and 1 indicates SFP1 The color of the lights indicates the following Green host good module good Red ho...

Page 52: ...cted to VeeT or VeeR in the module 7 RS0 Rate Select 0 optionally controls SFP module receiver LVTTL I 8 Rx_LOS 3rd Receiver Loss of Signal Indication In FC designated as Rx_LOS and in Ethernet designated as Signal Detect LVTTL O 9 RS1 Rate Select 1 optionally controls SFP module transmitter LVTTL I 10 VeeR Receiver Ground 11 VeeR Receiver Ground 12 RD Inverse Received Data Out CML O 13 RD Receive...

Page 53: ...10 J8 5 SFP0_SDA U6 H8 J8 4 SFP0_TXDISABLE U6 H9 J8 3 SFP0_TXFAULT U6 J8 J8 2 SFP0_MOD_ABS U6 G9 J8 6 SFP0_RS0 U6 J13 J8 7 SFP0_RS1 U6 J11 J8 9 SFP0_RX_LOS U6 H13 J8 8 SFP Channel 1 SFP1_TXP U6 B1 J5 18 SFP1_TXN U6 B2 J5 19 SFP1_RXP U6 B6 J5 13 SFP1_RXN U6 B5 J5 12 SFP1_SCL U6 H12 J5 5 SFP1_SDA U6 G14 J5 4 SFP1_TXDISABLE U6 H14 J5 3 SFP1_TXFAULT U6 J10 J5 2 SFP1_MOD_ABS U6 H11 J5 6 SFP1_RS0 U6 F9 ...

Page 54: ...nnel applications The QSFP modules are hot pluggable Hot pluggable refers to plugging in or unplugging a module while the host board is powered Due to routing losses in the printed circuit board utilizing 40GSFP Cu over copper is limited 2 8 1 QSFP Circuit Diagram A single Quad Small factor Pluggable QSFP connectors are connected to the high speed GTX Transceivers on the FPGA Figure 9 QSFP Channel...

Page 55: ... pin assignments are listed in Table 13 Table 13 QSFP Pin Assignments Pin Number Symbol Description Logic Family 1 GND Ground 2 Tx2n Transmitter Inverted Data Input CML I 3 Tx2p Transmitter Non Inverted Data Input CML I 4 GND Ground 5 Tx4n Transmitter Inverted Data Input CML I 6 Tx4p Transmitter Non Inverted Data Input CML I 7 GND Ground 8 ModSelL Module Select LVTTL I 9 ResetL Module Reset LVTTL ...

Page 56: ...d Data Output CML O 26 GND Ground 27 ModPrsL Module Present LVTTL O 28 IntL Interrupt LVTTL O 29 Vcc Tx 3 3V Power supply transmitter 30 Vcc1 3 3V Power supply 31 LPMode Low Power Mode LVTTL I 32 GND Ground 33 Tx3p Transmitter Non Inverted Data Input CML I 34 Tx3n Transmitter Inverted Data Input CML I 35 GND Ground 36 Tx1p Transmitter Non Inverted Data Input CML I 37 Tx1n Transmitter Inverted Data...

Page 57: ... U6 D2 J11 2 QSFP_RX3p U6 C4 J11 14 QSFP_RX3n U6 C3 J11 15 QSFP_TX3p U6 B1 J11 33 QSFP_TX3n U6 B2 J11 34 QSFP_RX4p U6 B6 J11 25 QSFP_RX4n U6 B5 J11 24 QSFP_TX4p U6 A3 J11 6 QSFP_TX4n U6 A4 J11 5 QSFP_MODSELn U6 E10 J11 8 QSFP_RESETn U6 D10 J11 9 QSFP_LPMODE U6 F14 J11 31 QSFP_INTn U6 F13 J11 28 QSFP_MODPRSn U6 G12 J11 27 QSFP_SCL_FET U6 B11 J11 11 QSFP_SDA_FET U6 B12 J11 12 Note QSFP_TXp n pair is...

Page 58: ...an be configured to accept signals including PPS and IRIG B000 RS232 RS485 RS422 TTL 2 9 2 Connections between the FPGA and Time Synchronization Circuitry Signal Name FPGA U2 U3 RS485_RO U6 D23 U2 A6 RS485_DI U6 D24 U2 A3 RS485_ON U6 F22 U2 A8 RS485_TE U6 E23 U2 A2 RS485_REn U6 G22 U2 A5 RS485_DE U6 F23 U2 A4 RS232_T1IN U6 F12 U3 A4 RS232_R1OUT U6 D14 U3 A3 RS232_ON U6 D13 U3 A6 RS232_DIN U6 E13 U...

Page 59: ...stem Clock Oscillator Signal Name FPGA Oscillator CLK_DIMM_SYSp U6 AB11 X3 4 CLK_DIMM_SYSp U6 AC11 X3 5 or CLK_QDRIIP_SYSp U6 P23 X2 4 CLK_QDRIIP_SYSn U6 N23 X2 5 3 2 High Speed GTX Clocks Refer to the relevant sub section of this User Manual for a detailed description of the clocking resources 4 LED Indicators The DNPCIe_10G_K7_LL _QSFP Ethernet Packet Analysis Engine provides various LED s to in...

Page 60: ...ibution The DNPCIe_10G_K7_LL _QSFP Ethernet Packet Analysis Engine supports a wide range of technologies from legacy devices like serial ports to DDR3 SDRAM Ethernet Transceivers and GTX Transceivers on the Xilinx FPGA This wide range of technologies including the various FPGA power supplies requires a variety of power supplies These are provided on the DNPCIe_10G_K7_LL _QSFP Ethernet Packet Analy...

Page 61: ...H A R D W A R E D E S C R I P T I O N DNPCIe_10G_K7_LL _QSFP User Manual www dinigroup com 54 The mounting holes are connected to the ground plane and can be used to ground test equipment ...

Page 62: ...oup com 55 Appendix 1 Appendix A UCF File See the Customer Support Package USB Flash Drive for the Xilinx User Constraint Files UCF 2 Ordering Information Request quotes by emailing sales dinigroup com For technical questions email support dinigroup com Chapter 5 ...

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