P R O G R A M M I N G / C O N F I G U R I N G T H E H A R D W A R E
DNPCIe_10G_K7_LL (_QSFP) User Manual
www.dinigroup.com
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8.
Power-cycle the board and verify that the “FPGA_DONE” blue LED (DS15)
is enabled, indicating successful configuration of the FPGA from BPI PROM.
3.4
Using multiple FPGA “boot” images
for configuration
fallback
In certain situations it may be desirable to store in the BPI flash multiple configuration
images for the FPGA. Multiboot has been tested in the context of Darklite reference
design build flow using Vivado and aetest host software.
Upon power-on flash starts being read at address zero where the golden image resides.
The golden image, before the start of fabric configuration bits - let's call this a header,
has a next address that points to the flash start address of the update image. Once the
configuration state machine reads this next address in the golden image header, it goes
to the flash address corresponding to the update image and starts reading configuration
header/and fabric bits from there. Both images contain a timer instruction in cclk clock
cycles (in hardware it is the same timer). If the FPGA is not configured by the time the
timer expires then the default image at address zero is loaded (the golden image). If the
update image is not there (or it fails to configure the FPGA in time) then configuration
falls back to golden image. There's multiple ways to trigger the fallback, one being
timeout, the others being CRC/IDCODE or address wraparound (for BPI) errors at the
end of bitstream programming.
