I N T R O D U C T I O N
DNPCIe_10G_K7_LL (_QSFP) User Manual
www.dinigroup.com
3
utilized. As with the QDRII+ SRAM, the only real limitation is the amount of time and
effort spent customizing the DDR3 memory controller to your needs.
1.6
PCI Express
–
Customizable 4-lane, GEN2 PCI Express
PCI Express is connected directly to the FPGA via 4-lanes of GTX transceivers. The
interfaces are GEN2 capable, and the board is shipped with PCIe IP that is a full
function, fixed, 4-lane master/target. To gain access to the PCIe interface, this IP must
be integrated with the user application. Dini Group provides support with the IP,
including BAR sizes. Additionally we can optionally add or subtract DMA engines,
scratchpad memories, interrupts, and other host-related functions to maximize the
performance, while utilizing the minimum FPGA resources. 'C' source for drivers for
several operating systems are included no charge. Partial reconfiguration of the FPGA is
supported via the PCIe interface.
1.7
Time Synchronization
The time code input allows for precise message time stamping and tracking. This input
can receiver PPS, or IRIG-B000 (RS232, RS485, RS422, TLL).
1.8
How Everything Works …
With direct data feeds such as NASDAQ (
ITCH
/
OUCH
) or Financial Information
Exchange (
FIX
), the
DNPCIe_10G_K7_LL (_QSFP)
contains all of the basic
functions required to minimize the amount of time it takes to receive Ethernet packets,
process them, and respond deterministically. The MAC, operating system et al, can be
bypassed. There are no interrupts. No operating system. Not a single clock cycle is
wasted here, enabling a near theoretical minimum in-to-out response time. For
algorithms requiring processing, FPGA resources can be hard coded to perform the
task. This includes real-time Monte Carlo analysis and floating point, all operating 1000's
of times faster than possible in a processor-based approach.
