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List of Figures
Figure 1 - DNPCIe_10G_K7_LL (_QSFP) Ethernet Packet Analysis Engine. (upper picture is the DNPCIe_10G_K7_LL and lower picture is the
DNPCIe_10G_K7_LL_QSFP) ..................................................................................................................................................................................................................4
Figure 2 - USB Flash Drive Directory Structure...........................................................................................................................................................................................................9
Figure 3
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DNPCIe_10G_K7_LL (_QSFP)
Block Diagram – Note the two SFP+ modules are replaced with one QSFP+ module in the _QSFP version ....... 26
Figure 4 –FPGA Serial Port............................................................................................................................................................................................................................................ 29
Figure 5 - QDR II+ Memory Architecture ................................................................................................................................................................................................................. 30
Figure 6 –FPGA Serial Port............................................................................................................................................................................................................................................ 41
Figure 7 - SFP+ Channel 0 Interface ........................................................................................................................................................................................................................... 44
Figure 8 – SFP+ GTX Oscillator .................................................................................................................................................................................................................................. 44
Figure 9 - QSFP+ Channel 0 Interface ........................................................................................................................................................................................................................ 47
Figure 10 – QSFP+ GTX Oscillator ............................................................................................................................................................................................................................ 48