ADSP-BF526 EZ-Board Evaluation System Manual
1-17
Using The ADSP-BF526 EZ-Board
configured automatically each time the processor is reset. The values are
used whenever SDRAM is accessed through the debugger (for example,
when viewing memory windows or loading a program).
To disable the automatic setting of the SDRAM registers, do one of the
following:
• CCES users, choose
Target > Settings > Target Options
and clear
the
Use XML reset values
check box.
• Vi+ users, choose
Settings > Target Options
and clear
the
Use XML reset values
check box.
For more information on changing the reset values, refer to the online
help.
An example program is included in the EZ-Board installation directory to
demonstrate how to setup and access the SDRAM interface. For more
information on how to initialize the registers after a reset, search the
online help for “reset values”.
Parallel Flash Memory Interface
The parallel flash memory interface of the ADSP-BF526 EZ-Board con-
tains a 4 MB (2M x 16 bits) 1.8V Numonyx M58WR032KB chip. Flash
memory connects to the 16-bit data bus and address lines 1 through 19.
Chip enable is decoded by the
AMS0—3
select lines through NAND and
AND gates. The address range for flash memory is
0x2000 0000
to
0x203F FFFF
.
Flash memory is pre-loaded with boot code for the blink and
power-on-self test (POST) programs. For more information, refer to
“Power-On-Self Test” on page 1-37
. Flash memory also is preloaded with
configuration flash information, which contains board revision, BOM
revision, and other data.
