ADSP-BF526 EZ-Board Evaluation System Manual
2-17
ADSP-BF526 EZ-Board Hardware Reference
The OTP memory writes require a precise 7V supply, which is turned on
by setting high the
OTP_FLAG_1P8V
signal. The OTP flag is connected to
the processor by setting positions 2 and 6 of
SW20
to
OFF
and position 5
ON
.
These settings connect the
PG13
flag pin of the processor to the shutdown
pin of the precise 7V circuit
VR9
.
The
USB_VRSEL
provides 5V to a device connected over the USB OTG
interface when running in host mode. A connection to the
USB_VRSEL
sig-
nal is set by the
SW13
switch (positions 2 and 5
OFF
and position 6
ON
).
Then the
PG13
programmable flag pin of the processor can be used to con-
trol the p-channel mosfet (
U23
). Refer to
for more information.
Table 2-11. GPIO Enable Switch (SW20)
SW20 Position
(Default)
From
To
Function
1 (
ON
)
Push button 1
(
SW19
)
Processor
(
U1
,
PG0
)
ON
(
PB1
)
OFF
(
UART1
CTS
U21
, host connector
P9.12
,
expansion interface II
P2.37
,
P4.37
,
J1.52
)
2 (
ON
)
Push button 2
(
SW15
)
Processor
(
U1
,
PG13
)
ON
(
PB2
)
OFF
(host connector
P9.8
, OTP flag for writes
SW20.8
, OTG voltage select
SW13.7
, expansion
interface II
P2.40
,
P4.40
,
J1.53
)
3 (
OFF
)
Power down push
button
(
SW16
)
Processor
(
U1
,
PG12
)
OFF
(
LED2
not driven by the power down push
button)
ON
(
SW16
drives
PG12
)
4 (
OFF
)
Wake push but-
ton (
SW17
)
Processor
(
U1
,
PG15
)
ON
(connects the wake push button
SW17
to
PG15
)
5 (
OFF
)
OTP_FLAG_1P8V
(
U3
)
Processor
(
U1
,
PG13
)
ON
(
PG13
controls the OTP flag for OTP
writes)
Requires
SW20.2
OFF
,
SW20.6
OFF
, and
JP16
installed
6 (
OFF
)
USB_VRSEL
(
U23
)
Processor
(
U1
,
PG13
)
ON
(
PG13
controls
USB_VRSEL
PG13
for OTG
host power)
Requires
SW20.2
OFF
and
SW20.5
OFF
